Memory Chip Flag Register Random Code Detection
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Solution Overview
Problem
Power failures during the erasing process of memory chips can cause the stored data of flag registers to become random code, leading to errors in reading and writing addresses.
Innovation Solution
The proposed solution involves an operating method for a memory chip that includes constructing the chip with at least two groups of nonvolatile registers, each containing a flag register and data registers. The method involves obtaining the stored data of the flag registers, judging whether it is random code, and if so, erasing all nonvolatile registers to eliminate the random code caused by power failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power failure occurs during erasing process, then data in flag register becomes random code, but this causes errors in reading and writing addresses
Solution Approach 1:
The patent applies preliminary action by checking the flag register data before performing read/write operations. The system proactively detects random code caused by power failure and prevents subsequent address errors, rather than waiting for errors to occur. This is implemented through the judgment step that examines flag register values before allowing normal operations to proceed.
Solution Approach 2:
The patent converts the harmful effect of power failure (which creates random code in flag registers) into a beneficial detection mechanism. By designing the flag register to contain specific patterns under normal conditions, any deviation from these patterns automatically signals power failure, turning a harmful randomization effect into a useful error detection signal.
2Reliability
If flag register data is not checked, then power failure errors go undetected, but checking adds operational complexity
Solution Approach 1:
The system performs self-service by automatically checking its own flag register data without requiring external intervention. The memory chip autonomously detects power failure conditions by examining its internal flag registers, and automatically prevents erroneous operations, reducing the need for complex external error handling mechanisms.
Solution Approach 2:
The patent implements feedback by using the flag register data to control subsequent operations. The system continuously monitors flag register values and uses this feedback to determine whether to proceed with read/write operations or to initiate error handling routines, creating a closed-loop error prevention mechanism.
Data Source
AI summary
The present application discloses a memory chip, an operating method thereof, and a judging method. The operating method of the memory chip includes steps of: constructing the memory chip including at least two nonvolatile register groups, wherein each of the nonvolatile register groups includes a flag register and at least one register, and stored data of each of flag registers is configured to indicate at least one storage state of the at least one register in a same one of the nonvolatile register groups. obtaining the stored data of at least one of the flag registers; judging whether the stored data of the at least one of the flag registers is random code; and erasing all of the nonvolatile registers if the stored data of the at least one of the flag registers is the random code.