Storage Class Memory Chip Grouping for DDR-Compatible Two-Level ECC
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Solution Overview
Problem
The challenge is to improve the reliability and minimize the access latency of Storage Class Memory (SCM) while ensuring compatibility with the Double Data Rate (DDR) protocol, as current SCM implementations face uncertainty in access latency and low universality due to built-in controller-based error correction.
Innovation Solution
A two-level memory error correction mechanism is employed, dividing memory chips into groups with first-type and second-type chips, where first-type chips store data and retry error correction codes, and second-type chips store running error correction codes, allowing for first- and second-level corrections to ensure high reliability and minimize latency, while meeting DDR protocol requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a built-in controller-based error correction mechanism is used in SCM, then data reliability is improved, but access latency increases and becomes uncertain
Solution Approach 1:
The patent segments the memory system into multiple memory chips organized in groups, with dedicated ECC chips for error correction. This segmentation allows parallel processing of data and error correction codes, reducing the time penalty associated with error correction while maintaining data reliability.
Solution Approach 2:
The patent pre-calculates and stores multiple levels of error correction codes (first-level ECC and second-level ECC) alongside the data before access operations. This preliminary preparation enables faster error correction during access operations, as the correction codes are already available and do not need to be computed in real-time, thus reducing access latency.
2Reliability
If a built-in controller-based error correction mechanism is used in SCM, then data reliability is improved, but compatibility with DDR protocol deteriorates
Solution Approach 1:
The patent designs the memory system with a standardized interface architecture that can operate with or without the built-in controller-based error correction mechanism. The memory chips and ECC chips can be configured in different modes to support both traditional DDR protocol operations and the enhanced error correction functionality, making the system universally compatible while maintaining reliability improvements.
3Reliability
If high-complexity error correction algorithms are used in built-in controller, then data reliability is improved, but access latency increases
Solution Approach 1:
The patent implements a tiered error correction approach where first-level ECC provides basic error correction for common errors, and second-level ECC provides additional correction for more complex error patterns. This partial application of different correction levels allows the system to handle most errors with the faster first-level correction, while only invoking the more complex second-level correction when necessary, thus balancing reliability with access latency.
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AI summary
A storage class memory, a data processing method, and a processor system are disclosed, and relate to the computer field. A plurality of memory chips included in the storage class memory are divided into at least one group. Each group includes a first-type memory chip and a second-type memory chip. The second-type memory chip is configured to store running error correction code, and the first-type memory chip is configured to store data and retry error correction code. The running error correction code is for performing first-level memory error correction on the data stored in the first-type memory chip in the same group. The retry error correction code is for performing, when the first-level memory error correction fails, second-level memory error correction on the data stored in the first-type memory chip. A two-level memory error correction mechanism is used to ensure high reliability of data stored in the storage class memory and minimize an access latency. In addition, the memory chips of the storage class memory are arranged, so that a bit width of the storage class memory meets a memory bit width indicated by a DDR protocol, and the storage class memory is compatible with the DDR protocol.