3D Memory Chip Guard Structure for Stress Crack Prevention
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Solution Overview
Problem
The manufacturing process of three-dimensional nonvolatile memory devices faces challenges such as chip stress-induced cracks and defects in the overlay vertical key formed on the scribe region, which affect the reliability and yield of the memory devices.
Innovation Solution
The solution involves forming chip guard patterns in the chip guard region between the main chip region and the scribe region, and creating a buffer slit in the space between the chip guard patterns. This structure helps to alleviate stress and prevent defects during the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip guard patterns are formed in the chip guard region, then stress is alleviated and cracks are prevented, but device structure becomes more complex
Solution Approach 1:
The chip guard region is segmented into multiple chip guard patterns arranged in a specific configuration. By dividing the protective structure into multiple discrete patterns rather than a continuous structure, the design achieves stress distribution and crack prevention while maintaining manageable structural complexity.
Solution Approach 2:
The chip guard patterns act as intermediary structures between the main chip region and the scribe region. These patterns serve as a buffer zone that mediates stress transfer, preventing cracks from propagating into the main chip area while the buffer slit provides additional stress relief.
2Productivity
If buffer slit is formed between chip guard patterns, then manufacturing yield is improved by preventing defects, but manufacturing process becomes more complex
Solution Approach 1:
The buffer slit is formed as part of the preliminary structuring process, creating stress relief pathways before subsequent manufacturing steps. By establishing this defect-prevention feature early in the manufacturing sequence, the design prevents crack propagation and overlay issues before they can affect yield-critical areas.
Solution Approach 2:
The buffer slit provides localized stress relief specifically in the chip guard region where stress concentration occurs during manufacturing. This localized quality enhancement addresses manufacturing yield issues at the critical interface region without requiring complex modifications throughout the entire device structure.
Data Source
AI summary
The present technology relates to a memory device and a method of manufacturing the same. A memory device according to an embodiment of the present disclosure includes a main chip region, a chip guard region disposed adjacent to the main chip region, a plurality of chip guard patterns formed in the chip guard region, and a buffer slit formed in a space between the plurality of chip guard patterns.