Impedance Calibration in Stacked Semiconductor Memory Chips
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Solution Overview
Problem
Current semiconductor devices, such as flash memory systems, face challenges in efficiently calibrating the impedance of output buffer circuits during read operations, which can lead to instability and reduced data transfer reliability, especially when multiple memory chips are stacked and operate independently.
Innovation Solution
Incorporating a calibration control circuit and a resistance element within each semiconductor chip to calibrate the impedance of the output buffer circuit during the busy state of the read operation, allowing for independent and noise-suppressed calibration without affecting other memory chips, and optionally using a temperature sensor to adjust resistance values for precise calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are stacked and operate independently, then device capacity and integration are improved, but impedance calibration reliability deteriorates due to noise interference and synchronization issues
Solution Approach 1:
The patent divides the impedance calibration function into separate calibration control circuits for each memory chip. Each chip has its own calibration control circuit that operates independently, allowing simultaneous calibration without interference between chips. This segmentation resolves the reliability issue in stacked configurations by eliminating cross-chip noise interference.
Solution Approach 2:
The patent performs impedance calibration during the busy state of read operations by incorporating calibration control circuits that can operate concurrently with data read operations. The calibration is initiated before the read operation completes, allowing the calibration to finish during the busy state without delaying the read operation. This preliminary action ensures calibration reliability in multi-chip stacked devices.
2Loss of time
If impedance calibration is performed during read operations, then calibration timing is improved, but operation speed deteriorates due to calibration overhead
Solution Approach 1:
The patent enables continuous calibration operation during read operations by using dedicated calibration control circuits that can operate simultaneously with data read operations. The calibration control circuit initiates calibration during the busy state, and the calibration process continues in parallel with the read operation without blocking either function. This continuity maintains both timely calibration and high operation speed.
Solution Approach 2:
The patent starts impedance calibration before the read operation completes by incorporating calibration control circuits that can be activated during the busy state. The calibration is initiated in advance and completes during the read operation's busy state, eliminating the need to wait for read completion before calibrating. This preliminary action minimizes timing loss while maintaining operation speed.
3Measurement precision
If calibration control circuits are added to each memory chip, then calibration precision is improved, but device complexity increases
Solution Approach 1:
The patent designs calibration control circuits that serve multiple functions: they control impedance calibration during read operations, manage calibration timing, and coordinate with the output buffer circuit. By making the calibration control circuit multi-functional, the patent achieves high calibration precision without proportionally increasing device complexity, as the same circuit performs multiple calibration-related tasks.
Solution Approach 2:
The patent merges the calibration control function with the existing output buffer circuit structure by integrating the calibration control circuit into the chip architecture. The calibration control circuit shares resources and timing control with the output buffer circuit, reducing the overall complexity increase. This merging approach allows precise impedance calibration while minimizing the added complexity from incorporating new calibration functionality.
Data Source
AI summary
A method for controlling a memory system, including a controller chip and a non-volatile memory chip which includes a calibration control circuit, a first output buffer, and a first resistance element, includes receiving a read command from the controller, setting a ready/busy signal to a busy state based on the read command, executing a calibration operation which controls an impedance of the first output buffer based on the read command, setting the ready/busy signal to a ready state, and sending data to the control chip in response to the read command. The calibration control circuit calibrates the impedance of the first output buffer circuit by using the first resistance element within a period in which the ready/busy signal is the busy state.