Memory Chip Output Impedance Calibration Using a Reference Chip
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Solution Overview
Problem
Current memory systems with NAND flash memory require lengthy calibration operations for output impedance, which can be time-consuming and inefficient, especially when calibrating multiple semiconductor storage devices.
Innovation Solution
A semiconductor device architecture that includes a reference resistor and a controller to perform ZQ calibration and subsequent chip calibration operations, utilizing replica buffer circuits and output buffer controllers to adjust output impedance, allowing for parallel calibration of multiple chips and reducing overall calibration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional ZQ calibration operation is performed for each semiconductor storage device, then output impedance precision is improved, but calibration time increases significantly
Solution Approach 1:
The calibration process is segmented into two distinct phases: ZQ calibration performed once on a reference chip to establish precise impedance characteristics, and subsequent chip calibration performed on all chips including the reference chip to propagate calibration data. This segmentation allows the time-consuming precision calibration to be performed only once rather than repeatedly on each chip.
Solution Approach 2:
The reference chip undergoes ZQ calibration in advance to establish accurate output impedance characteristics before other chips are calibrated. The calibration data and impedance information from the reference chip are then used to guide the subsequent chip calibration process, eliminating the need to perform full ZQ calibration on each individual chip.
2Measurement precision
If multiple semiconductor storage devices are calibrated sequentially, then calibration precision is maintained, but overall calibration time increases
Solution Approach 1:
The calibration characteristics and impedance data from the reference chip are copied and applied to all subsequent chips through the subsequent chip calibration process. Instead of performing independent calibration on each chip, the system uses the reference chip's calibrated parameters as a template, significantly increasing calibration throughput while maintaining precision.
Solution Approach 2:
The subsequent chip calibration mechanism serves multiple functions: it calibrates all chips including the reference chip, propagates impedance information from the reference chip to other chips, and maintains calibration precision across the entire system. This multi-functional approach eliminates the need for separate calibration operations on each chip.
3Loss of time
If parallel calibration of multiple chips is implemented, then calibration time is reduced, but system complexity increases
Solution Approach 1:
The parallel calibration capability is achieved by segmenting the calibration roles into a reference chip and subsequent chips, where the reference chip provides calibration data and subsequent chips receive and apply this data. This clear segmentation enables parallel operation without requiring complex coordination between multiple independent calibration systems.
Solution Approach 2:
The reference chip acts as an intermediary that mediates the calibration process between the calibration controller and all other chips. It performs the ZQ calibration once and then serves as the source of calibration data for subsequent chip calibration, simplifying the overall system architecture compared to having each chip perform independent calibration.
4Productivity
If additional calibration circuits are added to enable parallel calibration, then calibration efficiency is improved, but device complexity and cost increase
Solution Approach 1:
The subsequent chip calibration mechanism is designed to be universal and multi-functional, serving all chips including the reference chip through a single calibration process. This eliminates the need for additional dedicated calibration circuits for each chip, as the same calibration infrastructure is reused across all devices, maintaining calibration efficiency without increasing circuit complexity.
Solution Approach 2:
The reference chip performs self-calibration through ZQ calibration, and then all subsequent chips perform self-calibration using the reference chip's data. This self-service approach eliminates the need for external calibration equipment or additional complex control circuits, achieving high calibration efficiency with minimal added complexity.
Data Source
AI summary
A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.