Memory Chip Interconnection Routing for Bandwidth Utilization
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Solution Overview
Problem
The existing memory system faces a development bottleneck due to low effective utilization of memory bandwidth and high power consumption, primarily because of the time delay in processing memory access requests and inefficient data transmission.
Innovation Solution
A memory access processing method that utilizes a high-speed bus interface and chip interconnect interfaces to route memory access requests between memory chips, allowing the memory controller to send requests to available chips, even if the target chip is busy, thereby reducing transmission delays and improving bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If one memory access request is processed by one subarray in one memory chip, then power consumption is reduced, but time delay increases
Solution Approach 1:
The patent segments memory access requests into multiple secondary requests and distributes them across multiple memory chips. The memory controller divides a primary memory access request into at least two secondary memory access requests, which are then sent to different memory chips simultaneously. This segmentation allows parallel processing of memory operations across multiple chips, reducing the overall time delay while maintaining power efficiency by activating only the necessary chips for each access pattern.
Solution Approach 2:
The patent introduces chip interconnect interfaces that enable memory chips to communicate directly with each other, creating a new dimensional pathway for data transmission. This chip-to-chip interconnection architecture adds a spatial dimension to memory access, allowing requests to be routed across multiple chips without all chips needing to be activated simultaneously, thus reducing both time delay and power consumption.
2Reliability
If memory controller waits for response from target memory chip before sending next request, then data accuracy is ensured, but bandwidth utilization decreases
Solution Approach 1:
The patent implements preliminary action by having the memory controller send multiple secondary memory access requests to different memory chips in parallel before receiving responses. Instead of waiting for each response sequentially, the controller pre-issues multiple requests to different chips simultaneously. This allows the system to maintain a continuous stream of memory operations, improving bandwidth utilization while ensuring data accuracy through proper response handling and synchronization mechanisms.
3Productivity
If memory access requests are evenly distributed to all memory chips, then bandwidth utilization improves, but power consumption increases
Solution Approach 1:
The patent applies local quality by enabling each memory chip to independently determine whether it is the target chip for a given memory access request. Each chip has the capability to evaluate its own relevance to incoming requests and selectively activate or deactivate its subarrays based on local conditions. This localized decision-making allows the system to achieve good bandwidth utilization by directing requests to appropriate chips while minimizing power consumption by keeping non-target chips in low-power states.
Data Source
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AI summary
Embodiments of the present invention disclose a memory access processing method based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present invention includes: receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule through a chip interconnect interface, the memory access request to the target memory chip corresponding to the memory access request. Embodiments of the present invention are mainly used in a process of processing a memory access request.