3D Memory Chip Interlayer Channel Test Compression
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Solution Overview
Problem
In multi-chip systems, particularly those with a 3D stacked structure, existing test methods are inefficient and time-consuming, affecting productivity and fabrication costs due to the need for comprehensive testing of memory devices across multiple chips.
Innovation Solution
A multi-chip system with integrated test circuits and interlayer channels that precharge and transmit test result signals, allowing for simultaneous testing of multiple memory chips by compressing multi-bit data into one-bit or more, with the interlayer channel levels indicating error status, facilitating faster and more efficient testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If compression test (parallel test) is performed on multiple memory chips, then test time is reduced, but test complexity and difficulty of detecting errors increase
Solution Approach 1:
The patent divides the test system into multiple independent test channels, each capable of independently testing a subset of memory chips. Each test channel has its own test circuit and can operate independently, allowing the overall test to be segmented into manageable units that reduce complexity while maintaining parallel testing capabilities.
Solution Approach 2:
The patent introduces intermediary components including test circuits that generate test patterns, compress test data, and generate test result signals. These intermediary elements facilitate the compression test by managing the complexity of parallel testing across multiple chips through structured signal generation and processing.
2Quantity of substance
If 3D stacked structure with multiple memory chips is used, then integration degree and capacity increase, but test complexity and time increase
Solution Approach 1:
The patent merges multiple memory chip tests into a single compression test operation by writing the same test data to corresponding cells across multiple chips and reading them back simultaneously. This combining approach allows testing of stacked memory structures to be performed in parallel, reducing overall test time while maintaining high integration capacity.
Solution Approach 2:
The patent performs preliminary actions by pre-charging interlayer channels before test data transmission and preparing test patterns in advance. These preliminary steps ensure that the compression test can proceed efficiently without delays during the actual testing phase, reducing overall test time for high-capacity stacked structures.
3Productivity
If interlayer channels are used to transmit test signals between stacked chips, then test efficiency improves, but signal transmission complexity increases
Solution Approach 1:
The patent makes interlayer channels multi-functional by using them for both normal memory operation and test signal transmission. The same physical channels serve dual purposes, reducing the need for dedicated test channels and thereby reducing overall system complexity while maintaining high test efficiency through parallel testing capabilities.
Data Source
AI summary
An integrated circuit chip includes a test circuit suitable for performing a test operation and generating a test result signal indicating whether there is an error or not in the integrated circuit chip, a transmitting unit suitable for transmitting the test result signal through an interlayer channel. The interlayer channel is precharged to a first level before the transmitting unit transmits the test result signal, and the interlayer channel is driven to a second level when there is an error.