Memory Chip Kill Interface with Write Shift Logic
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Solution Overview
Problem
Existing memory systems face inefficiencies due to chip failures and ionizing radiation-induced errors, which can lead to instability and require extensive processor real estate for redundant systems and complex memory remapping, failing to effectively correct soft errors.
Innovation Solution
A memory interface with write shift logic that identifies and bypasses a failing memory chip by shifting data away from the bad chip, using check bits for error correction and eliminating the need for redundant memory boards, thus maintaining system stability without excessive processor resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant memory boards are used to handle chip failures, then system reliability is improved, but device complexity and cost increase due to extra unused memory boards
Solution Approach 1:
The patent extracts and removes the need for redundant memory boards by implementing a chip kill mechanism that bypasses failed chips through software or hardware memory controller remapping. This eliminates the requirement for standby memory boards while maintaining system reliability through dynamic chip disabling and memory address remapping.
Solution Approach 2:
The memory controller is enhanced with multi-functionality to perform both normal memory access and chip kill operations. The same memory controller handles standard read/write operations as well as dynamic remapping when chips fail, eliminating the need for separate redundant memory boards and their associated control logic.
2Reliability
If memory remapping is implemented to bypass bad chips, then system stability is improved, but processor real estate increases due to extensive rerouting and management requirements
Solution Approach 1:
The patent segments the memory address space to accommodate chip kill operations. By dividing the memory address mapping into manageable segments that can be dynamically remapped, the system can bypass failed chips without requiring extensive rerouting logic across the entire processor, thus reducing the real estate required.
Solution Approach 2:
The patent introduces an intermediary layer in the memory controller that handles the remapping logic. This intermediary component manages the translation of memory addresses when chips are killed, offloading the complexity from the main processor silicon and reducing the real estate requirements on the processor itself.
3Reliability
If extensive rerouting and management of memory is performed in the memory controller, then chip failure handling is improved, but manufacturing cost increases due to expensive real estate on the processor
Solution Approach 1:
The memory system performs self-service by automatically detecting failed chips and dynamically remapping memory addresses without requiring external intervention or complex processor logic. The memory controller autonomously manages chip kill operations, reducing the need for expensive processor real estate and simplifying manufacturing.
Data Source
AI summary
A memory interface comprising a first data input for receiving a data line to be stored in memory, a bad chip register containing a bad chip value for identifying a bad memory chip of a memory device to be used with the memory interface, and a write shift logic circuit receiving the data line from the first data input. The data line contains a plurality of data bits and a plurality of check bits, the check bits being logically appended to one end of the data bits. The write shift logic, in response to the bad chip value, causes a portion of the data line to be shifted toward the one end of the bad memory chip.