Memory Error Correction With Chip Kill Detection and Repair
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Solution Overview
Problem
Memory technologies face challenges in storing and outputting data correctly when erroneous data is present or a failed memory cell exists, as existing methods are inefficient in detecting and correcting chip-level errors.
Innovation Solution
An error correction method and chip kill detection method that includes data error detection, random error correction, chip kill detection, and chip repair processes, utilizing error correction codes like BCH and RS codes, and parity checks to identify and correct errors, and relocate data from faulty chips to spare chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If random error correction is performed on all data from multiple chips, then data errors can be corrected, but it is difficult to identify which specific chip has a chip kill error
Solution Approach 1:
The patent segments the error correction process into two distinct phases: first performing random error correction on all chips collectively, then performing chip kill detection by individually testing each chip. This segmentation allows the system to handle both types of errors systematically without confusion between them.
Solution Approach 2:
The patent introduces an intermediary detection step between random error correction and final data output. This intermediary step involves individually reading and verifying data from each chip to identify chip kill errors, serving as a mediator that bridges the gap between collective error correction and specific fault identification.
2Difficulty of detecting and measuring
If chip kill detection is performed by individually testing each chip, then the faulty chip can be identified, but the process becomes complex and time-consuming
Solution Approach 1:
The patent performs preliminary random error correction on all chips before conducting chip kill detection. This preliminary action prepares the data by correcting random errors first, so that subsequent chip kill detection can focus solely on identifying stuck-at faults without interference from random errors, simplifying the overall detection logic.
Solution Approach 2:
The patent maintains continuity by performing both random error correction and chip kill detection on all chips without re-reading or re-transmitting data between steps. The data remains in the system throughout the process, allowing seamless transition from one detection phase to the next and eliminating redundant operations.
3Measurement precision
If data is re-read and re-transmitted multiple times for error detection, then accurate error identification can be achieved, but memory operation time increases
Solution Approach 1:
The patent performs both random error correction and chip kill detection in continuous operation without re-reading or re-transmitting data between steps. The data remains in the memory system throughout the detection process, allowing both types of errors to be identified in a single continuous operation rather than requiring multiple separate read-transmit cycles.
Data Source
AI summary
An error correction method and a chip kill detection method of a memory including a plurality of chips may be provided. The method may include a first data error detection step of detecting whether an error exists in data outputted from the plurality of chips. The method may include a random error correction step of correcting an error occurred in data when it is detected in the first data error detection step that an error exists. The method may include a chip kill detection step of determining, when an error occurs even after the random error correction step, that a chip kill error has occurred, and detecting a chip where the chip kill error has occurred, by correcting the error through assuming one chip among the plurality of chips as a chip where the chip kill error has occurred.