Shared-Node Memory Chip Isolation for Read Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory chips, such as DRAM chips, generate noise during reading operations due to signal reflection, which degrades data quality.
Innovation Solution
A memory device with a processor and chips connected via a node, where the processor adjusts the resistance of variable resistors in series with capacitors to control signal flow, minimizing noise by isolating non-active chips during reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are connected via a shared node to increase memory capacity, then the memory storage capability is improved, but noise interference is generated during read operations which degrades data quality
Solution Approach 1:
The memory system is segmented into multiple independent memory chips (first memory chip, second memory chip) that can be selectively activated. During read operations, only the active memory chip is enabled while the other is isolated, preventing noise interference. This segmentation allows multiple chips to coexist on the same bus without mutual interference during simultaneous operations.
Solution Approach 2:
The memory device employs dynamic resistance control where the resistance of inactive memory chips is adjusted in real-time based on operation mode. During read operations, the resistance of the inactive chip is increased to isolate it from the shared node, minimizing noise. This dynamic adjustment optimizes the system by adapting the electrical characteristics of each chip according to its operational state.
2Object-affected harmful factors
If the resistance of memory chips is adjusted dynamically to control signal flow, then noise interference is reduced, but the device complexity increases due to additional control mechanisms
Solution Approach 1:
The resistance control functionality is merged into the memory chip itself through integration of variable resistors and control circuits within each memory device. This eliminates the need for external resistance control circuits, reducing overall system complexity while maintaining the noise reduction capability. The controller manages both memory operations and resistance adjustments through unified control signals.
Solution Approach 2:
Each memory chip is equipped with self-controlled resistance adjustment capability. The memory chip autonomously adjusts its own resistance based on control signals from the controller, eliminating the need for external resistance control circuits. This self-service approach simplifies the overall system architecture while maintaining effective noise isolation.
3Measurement precision
If variable resistors are added in series with capacitors to control signal flow, then data signal quality is improved, but the manufacturing complexity increases
Solution Approach 1:
The invention utilizes variable resistors whose resistance can be dynamically changed between different states (high resistance for isolation, low resistance for signal transmission). This parameter change capability allows the same physical component to serve multiple functions: signal coupling during write operations and noise isolation during read operations, simplifying the overall circuit design while maintaining signal quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances data signal quality by reducing noise interference from inactive chips during read operations.
Implementation Method 1
The first variable resistor is coupled in series with the first capacitor. The processor is configured to increase a resistance of the second chip in response to reading the first data via the first node.
Data Source
AI summary
A memory device includes a first chip, a second chip and a processor. The second chip is coupled to the first chip at a first node. The second chip includes a first capacitor and a first variable resistor. The first capacitor is coupled to the first node. The first variable resistor is coupled in series with the first capacitor. The processor is coupled to the first node, and is configured to perform a first read operation to the first chip via the first node. A method for operating a memory device is also disclosed herein.