Memory Chip Pad Structure for Faster Inter-Chip Signal Transfer
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Solution Overview
Problem
Current semiconductor systems face challenges in transmitting signals quickly between semiconductor chips and integrated circuits, which limits their ability to process high-capacity data efficiently due to increased parasitic capacitance and signal delay.
Innovation Solution
The semiconductor system incorporates a structure with main and sub pads on each memory chip, where the main pads are connected to external interconnection structures for signal reception and the sub pads are connected via internal interconnection structures for data transmission between chips, differing in electrostatic discharge characteristics and size to minimize parasitic capacitance and enhance signal speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of semiconductor chips is increased to process high-capacity data, then data processing capacity is improved, but signal delay and parasitic capacitance increase
Solution Approach 1:
The pad structure is segmented into main pads and sub pads with distinct functions. Main pads interface with external interconnection structures for signal input, while sub pads connect to internal interconnection structures for data transmission between chips. This segmentation reduces parasitic capacitance by optimizing the electrical characteristics of each pad type, thereby reducing signal delay while maintaining high data processing capacity through multiple chips.
2Volume of moving object
If the feature size of semiconductor chips is decreased to reduce system volume, then system volume is reduced, but signal transmission performance deteriorates
Solution Approach 1:
Different regions of the chip are assigned different electrical characteristics through the main pad and sub pad structure. The main pads are optimized for external signal reception with appropriate electrostatic discharge characteristics, while sub pads are optimized for internal data transmission with lower parasitic capacitance. This local quality differentiation enables high-speed signal transmission within the compact chip structure without compromising overall system volume reduction.
Data Source
AI summary
In an embodiment of the disclosed technology, a semiconductor system may include a substrate; a first memory chip supported by the substrate, wherein the first memory chip includes a first main pad structured to be electrically connected to an interconnection structure disposed outside the first memory chip and a first sub pad electrically connected to the first main pad; and one or more second memory chips supported by the substrate, wherein each of the one or more second memory chips includes a second main pad structured to be electrically connected to an interconnection structure disposed outside the first memory chip and a second sub pad electrically connected to the second main pad, and the second main pad or the second sub pad included in one second memory chip of the one or more second memory chips is electrically connected to the first sub pad by a first internal interconnection structure.