Memory Chip Parallel Data Output Without Conversion Circuits
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Solution Overview
Problem
The memory-wall effect in high-performance computing and AI systems, where data transmission rates between logic circuits and DRAM chips are reduced due to the stacked structure of DRAM chips, leading to increased power consumption, clock latencies, and larger die areas, despite attempts to mitigate this with faster data rates or wider buses, which come with their own disadvantages.
Innovation Solution
A memory chip design that eliminates parallel-to-serial and serial-to-parallel circuits, using a memory bank with I/O data bus and sensing amplifiers to output data in parallel, along with a handshaking signal to manage refresh operations, and transceivers to receive and transmit data directly, allowing for parallel data transfer without the need for conversion circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If faster data rate (e.g., from DDR3 to DDR4 or DDR5) is used to transmit data between the DRAM chips and the logic circuit, then data transmission speed is improved, but cost increases (more expensive tester), noise margin decreases, and power consumption increases
Solution Approach 1:
The patent divides the data transmission path into multiple parallel channels (multiple bit lines connected to multiple sensing amplifiers), allowing data to be transmitted simultaneously through multiple paths. This segmentation enables high data throughput without requiring extremely high clock speeds, thus avoiding the power consumption and noise margin issues associated with single-channel high-speed transmission.
2Productivity
If wider data bus of the logic circuit and the wider data bus of the DRAM chips (e.g., HBM) is used to transmit data, then data transmission bandwidth is improved, but power consumption increases, die area increases, and TSV process cost increases
Solution Approach 1:
The patent transitions from a single-dimensional wide bus approach to a multi-dimensional parallel structure where multiple narrower bit lines operate simultaneously through stacked memory banks and multiple sensing amplifiers. This dimensional transformation achieves high bandwidth without requiring a single extremely wide bus, thereby reducing die area and avoiding expensive TSV processes.
3Adaptability or versatility
If parallel-to-serial circuit and serial-to-parallel circuit are used to enable faster data rate or wider data bus, then data transmission flexibility is improved, but clock latencies increase and power consumption increases
Solution Approach 1:
The patent extracts and eliminates the parallel-to-serial and serial-to-parallel conversion circuits from the data path. By designing the memory interface to natively support parallel data transmission from multiple sensing amplifiers directly to the logic circuit, the patent removes the latency-introducing conversion stages while maintaining transmission flexibility through configurable bit line connections.
Data Source
AI summary
A memory chip includes a memory bank, I/O data bus, and a first plurality of sensing amplifiers. The first plurality of sensing amplifiers are between the memory bank and the I/O data bus and configured to output a first plurality of data in parallel to the I/O data bus. There is no parallel-to-serial circuit and no serial-to-parallel circuit in the memory chip.