Memory Chip Parallel Data Transmission Without Serial Conversion
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Solution Overview
Problem
The memory-wall effect in memory systems for high-performance computing and AI systems occurs due to the mismatched scaling of DRAM chips and logic circuits, leading to reduced data transmission rates, increased power consumption, and larger die areas, despite efforts to improve data transmission through faster data rates or wider data buses, which introduce additional costs and inefficiencies.
Innovation Solution
The implementation of a memory system and chip design that eliminates parallel-to-serial and serial-to-parallel circuits, utilizing a memory bank with sensing amplifiers and a handshaking signal to manage refresh operations, allowing for parallel data transmission without the need for additional converting circuits, and includes a memory controller with a physical layer that supports direct parallel data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If faster data rate is utilized to transmit data between DRAM chips and logic circuit, then data transmission rate is improved, but cost increases and noise margin decreases
Solution Approach 1:
The patent extracts and eliminates the parallel-to-serial and serial-to-parallel converting circuits from the memory system. By removing these conversion circuits, the system achieves direct parallel data transmission between the memory chip and logic circuit, thereby avoiding the need for expensive high-speed serial interfaces while maintaining high data transmission rates.
Solution Approach 2:
Instead of converting parallel data to serial for transmission and then back to parallel (the conventional approach), the patent inverts the approach by transmitting data directly in parallel without conversion. This inversion eliminates the bottlenecks and costs associated with serial conversion while improving noise margin through parallel differential signaling.
2Speed
If wider data bus is utilized to transmit data between DRAM chips and logic circuit, then data transmission rate is improved, but power consumption increases and die area increases
Solution Approach 1:
The patent segments the data transmission into multiple independent parallel channels (e.g., 8-bit wide data bus divided into 8 separate signal lines). Each channel operates independently with its own differential pair, allowing for efficient power management and reduced overall power consumption compared to a single wide serial interface operating at high frequency.
3Adaptability or versatility
If parallel-to-serial circuit and serial-to-parallel circuit are utilized, then data transmission flexibility is improved, but clock latencies increase and power consumption increases
Solution Approach 1:
The patent removes the parallel-to-serial and serial-to-parallel conversion circuits from the data path. By eliminating these conversion stages, the system achieves direct parallel transmission between memory and logic circuit, thereby reducing clock latencies and power consumption while maintaining transmission flexibility through programmable data width selection.
4Quantity of substance
If stacked structures of DRAM chips are utilized, then memory capacity is improved, but data transmission rate between logic circuit and DRAM chips is reduced
Solution Approach 1:
The patent transitions from vertical stacking (3D stacked structures) to a planar arrangement where multiple DRAM chips are positioned side-by-side on the same substrate. This dimensional change allows each chip to maintain direct, short-distance parallel connections to the logic circuit, preserving high data transmission rates while achieving increased total memory capacity through horizontal expansion rather than vertical stacking.
Data Source
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AI summary
A memory chip includes a memory bank, I/O data bus, and a first plurality of sensing amplifiers. The first plurality of sensing amplifiers are between the memory bank and the I/O data bus and configured to output a first plurality of data in parallel to the I/O data bus. There is no parallel-to-serial circuit and no serial-to- parallel circuit in the memory chip.