Memory Chip Parallel I/O Architecture Without Data Conversion
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Solution Overview
Problem
The memory-wall effect in high-performance computing and AI systems, where data transmission rates between logic circuits and DRAM chips are reduced due to the stacked structure of DRAM chips, leading to increased power consumption, clock latencies, and larger die areas, despite attempts to use faster data rates or wider data buses, which come with their own disadvantages.
Innovation Solution
A memory chip design that eliminates the need for serial-to-parallel and parallel-to-serial converting circuits by using a memory system with a first align circuit and transceivers that allow parallel data transmission between the memory and logic circuit, matching the width of the I/O data bus to the data width, and utilizing a control signal to adjust the number of sensing amplifiers and bit switches for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If faster data rate (e.g., DDR4 or DDR5) is used to transmit data between DRAM chips and logic circuit, then data transmission speed is improved, but cost increases due to more expensive tester, less noise margin, and other disadvantages
Solution Approach 1:
The patent extracts and removes the serial-to-parallel and parallel-to-serial converting circuits from the memory system. By eliminating these converting circuits, the system achieves direct parallel data transmission between the memory chip and logic circuit, avoiding the need for higher-speed serial interfaces like DDR4/DDR5 that require expensive testing and have poor noise margins. This extraction principle resolves the contradiction by maintaining high speed through parallel transmission while avoiding the manufacturing costs associated with fast serial interfaces.
2Productivity
If wider data bus (e.g., HBM) is used to transmit data between DRAM chips and logic circuit, then data transmission capacity is improved, but power consumption increases and die area becomes larger
Solution Approach 1:
The patent removes the unnecessary serial-to-parallel and parallel-to-serial converting circuits that consume power and occupy die area. By enabling direct parallel data transmission, the system achieves high data transmission capacity equivalent to wide data bus interfaces without requiring the physical wide bus infrastructure. This eliminates the power consumption and die area penalties associated with HBM-style wide data buses while maintaining high productivity.
3Adaptability or versatility
If serial-to-parallel circuit and parallel-to-serial circuit are used for data conversion, then data transmission compatibility is improved, but clock latencies increase and power consumption increases
Solution Approach 1:
The patent extracts and eliminates the serial-to-parallel and parallel-to-serial converting circuits from the data path. By removing these conversion stages, the system achieves direct parallel data transmission between memory and logic circuit, eliminating the clock latencies and power consumption associated with data format conversion. Compatibility is maintained through the align circuit that ensures proper data alignment without requiring serial conversion.
Solution Approach 2:
The align circuit performs multiple functions: it aligns data from multiple memory banks, ensures proper data formatting, and enables direct parallel transmission without serial conversion. This multi-functional align circuit replaces the need for separate serial-to-parallel and parallel-to-serial converters, achieving universal compatibility while reducing latency and power consumption.
4Quantity of substance
If stacked structures of DRAM chips are used, then memory density is improved, but data transmission rate between logic circuit and DRAM chips is reduced due to memory-wall effect
Solution Approach 1:
The patent transitions from serial/dimensional data transmission to parallel data transmission across multiple data lines. By utilizing multiple memory banks and their associated sensing amplifiers to simultaneously transmit data in parallel, the system overcomes the memory-wall effect inherent in stacked DRAM architectures. This dimensional change from serial to parallel transmission maintains high memory density while achieving high data transmission rates.
Data Source
AI summary
A memory chip includes a memory bank, an I/O data bus, and a first plurality of sensing amplifiers. The first plurality of sensing amplifiers is configured to parallelly output a first plurality of data. A width of the I/O data bus is equal to a width of the first plurality of data parallelly outputted by the first plurality of sensing amplifiers.