Stacked Memory Chip Pumping Signal Delay for Power Stability
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Solution Overview
Problem
In semiconductor integrated circuits with stacked memory chips, it is challenging to predict the timing of power-up signal generation due to process variations, leading to increased power consumption and potential operational failures from unstable power delivery when all chips perform pumping operations simultaneously.
Innovation Solution
A semiconductor integrated circuit design that includes a pumping enable signal control unit in each memory chip to generate and delay a pumping enable signal based on a power-up or trigger signal from an adjacent chip, allowing sequential pumping operations across stacked memory chips, thereby reducing simultaneous power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory chips perform pumping operations simultaneously, then power-up signal generation is achieved, but power consumption increases and power stability deteriorates
Solution Approach 1:
The patent segments the simultaneous pumping operations of multiple memory chips into sequential operations by introducing a delay mechanism. The first memory chip performs pumping operation immediately upon detecting the power-up signal, while subsequent memory chips delay their pumping operations by predetermined time periods, thereby distributing power consumption over time and improving power stability.
Solution Approach 2:
The patent applies preliminary action by having the first memory chip perform its pumping operation before the other memory chips. This sequential arrangement ensures that the initial power-up signal is processed by one chip first, and subsequent chips follow in a predetermined sequence, preventing simultaneous power consumption spikes.
2Use of energy by moving object
If pumping operations are performed sequentially with delays, then power consumption is reduced, but operation time increases
Solution Approach 1:
The patent applies partial action by implementing delay periods only for the second and subsequent memory chips, while the first memory chip performs its pumping operation immediately without delay. This selective approach reduces overall power consumption while minimizing the impact on total operation time, as the critical first operation is not delayed.
Data Source
AI summary
Provided is a semiconductor integrated circuit including a plurality of memory chips stacked therein, Each of the memory chips may include: a pumping enable signal control unit suitable for generating a pumping enable signal in response to a power-up signal or a trigger signal received from a first adjacent memory chip, delaying the pumping enable signal by a given time, and outputting the delayed pumping enable signal to a second adjacent memory chip; and a pumping unit suitable for generating a pumping voltage by performing a pumping operation in response to the pumping enable signal.