Stacked Memory Chip Refresh Address Inversion
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Solution Overview
Problem
Nonvolatile memory devices, such as DRAM, face issues with data retention due to electric charge loss over time, requiring frequent refresh operations to prevent data loss, which can generate power noise and heat, affecting product reliability.
Innovation Solution
A memory device with stacked memory chips, each equipped with a chip identifier generator, refresh counter, and refresh address generator, allowing for the inversion of target row addresses to distribute refresh operations across memory cell rows, thereby minimizing power noise and heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to prevent data loss, then data retention is improved, but power noise and heat generation increase
Solution Approach 1:
The patent inverts the target row address to generate the actual refresh row address. This inversion causes different memory chips to access different memory cell rows during refresh operations, distributing the refresh load and preventing concentration of power noise and heat in specific regions while still maintaining data retention across all chips.
2Quantity of substance
If multiple memory chips are stacked to increase capacity, then storage density is improved, but power noise and heat concentration worsens
Solution Approach 1:
By inverting the target row address, the patent ensures that memory chips stacked together access different memory cell rows during refresh operations. This spatial distribution of refresh activities across stacked chips prevents heat concentration and power noise accumulation, allowing higher storage density without compromising thermal management.
3Productivity
If refresh operations are performed on the same memory cell rows across all memory chips, then refresh efficiency is improved, but power noise and heat generation increase
Solution Approach 1:
The patent applies address inversion to distribute refresh operations across different memory cell rows in stacked memory chips. This approach maintains overall refresh efficiency by ensuring all chips perform refresh operations in parallel, while simultaneously reducing power noise and heat generation by preventing concentration of refresh activities in the same physical locations.
Solution Approach 2:
The patent segments the refresh operations across different memory cell rows in stacked chips through address inversion. Instead of all chips accessing the same rows, the inversion technique divides the refresh workload across multiple row segments, reducing localized power noise and heat while maintaining system-wide refresh efficiency.
Data Source
AI summary
A memory device is provided. The memory device includes a plurality of memory chips that are stacked, wherein each of the memory chips includes a memory cell array, which includes a plurality of memory cell rows, a chip identifier generator configured to generate a chip identifier signal indicating a chip identifier of each of the memory chips, a refresh counter configured to generate a target row address for refreshing the memory cell rows in response to a refresh command, and a refresh row address generator, which receives the chip identifier signal and the target row address and outputs one of the target row address and an inverted target row address, obtained by inverting the target row address, as a refresh row address based on the chip identifier signal, and performs a refresh operation on a memory cell row corresponding to the refresh row address.