Memory Chip Hierarchical Region Flag Testing
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Solution Overview
Problem
Memory chips often have limited spare memory regions for repairing defective areas, leading to reduced yield and efficiency in manufacturing due to inefficient use of repair resources.
Innovation Solution
A memory chip system that includes a peripheral unit capable of generating region flags and group flags through write and read operations to identify defective regions and determine the need for repair, allowing for targeted repair operations and efficient use of spare memory regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional test methods are used to identify defective regions, then manufacturing precision can be maintained, but test time and power consumption increase significantly
Solution Approach 1:
The memory chip is divided into multiple memory region groups, where each group contains several memory regions that can be accessed simultaneously. The peripheral unit generates region flags for each memory region and combines them into group flags, enabling hierarchical testing that reduces overall test time while maintaining identification accuracy.
Solution Approach 2:
Multiple memory regions that can be accessed at the same time are merged into a single memory region group. The peripheral unit performs write and read operations on entire groups simultaneously, generating group flags that represent the collective status of all regions in the group, thereby parallelizing the testing process.
2Manufacturing precision
If comprehensive testing of all memory regions is performed, then manufacturing precision is improved, but power consumption increases
Solution Approach 1:
The testing process is segmented into hierarchical levels: individual memory regions are tested and flagged, then region flags are combined to form group flags. This allows the system to focus power consumption on essential testing operations while maintaining comprehensive defect detection through the flag generation and combination process.
Solution Approach 2:
Memory regions accessible at the same time are merged into groups, allowing simultaneous testing operations. The peripheral unit generates group flags by combining region flags, enabling power-efficient batch processing of multiple regions without sacrificing detection accuracy.
3Reliability
If spare memory regions are used for repair, then reliability of defective regions is improved, but the limited quantity of spare regions reduces productivity
Solution Approach 1:
The testing system identifies defective regions at the finest granularity level by generating individual region flags, allowing precise localization of defects. This enables targeted repair strategies that maximize the utilization of limited spare memory regions by repairing only the specific defective areas rather than entire memory blocks.
Solution Approach 2:
The patent replaces physical inspection and manual repair assessment with an automated flag generation system. The peripheral unit automatically generates region flags and group flags through write and read operations, enabling rapid identification of defective regions and facilitating efficient allocation of spare memory regions for repair, thereby increasing manufacturing yield.
Data Source
AI summary
A memory chip includes a memory region group including a plurality of memory regions. The memory chip also includes a peripheral unit configured to generate region flags of the memory regions by performing write and read operations on the respective memory regions, each of the region flags indicating whether corresponding memory region is a defective region, and to generate a group flag indicating whether the memory region group needs to be repaired, based on the region flags.