3D Memory Chip Guard Layout for Scribe Stress Relief
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Solution Overview
Problem
The existing two-dimensional nonvolatile memory devices face limitations in integration and manufacturing yield due to mechanical stress and defects in the scribe region, which can lead to cracks and misalignment issues during the manufacturing process of three-dimensional memory devices.
Innovation Solution
The solution involves forming chip guard patterns in the chip guard region between the main chip and scribe regions and creating a buffer slit between the chip guard patterns to alleviate stress and prevent crack propagation, thereby enhancing the manufacturing process and structural stability of three-dimensional memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If chip guard patterns are formed in the chip guard region, then structural stability is improved, but device complexity increases
Solution Approach 1:
The chip guard region is segmented into multiple chip guard patterns arranged in parallel, which distributes and manages the structural reinforcement function across multiple discrete elements rather than a single continuous structure, thereby improving stability while maintaining manufacturability
Solution Approach 2:
The chip guard patterns act as intermediary structures between the main chip region and the scribe region, providing a transition zone that manages stress and prevents crack propagation without directly modifying the main chip structure or the scribe region
2Reliability
If a buffer slit is formed between chip guard patterns, then manufacturing yield is improved, but device complexity increases
Solution Approach 1:
The buffer slit segments the chip guard patterns by creating spacing between them, which prevents stress concentration and crack propagation between adjacent patterns, thereby improving manufacturing yield while adding minimal structural complexity
Solution Approach 2:
The buffer slit serves as a pre-designed stress relief zone that cushions against potential crack propagation between chip guard patterns during manufacturing processes, addressing potential failures before they occur
3Reliability
If chip guard patterns and buffer slit are added to alleviate stress, then reliability is improved, but ease of manufacture deteriorates
Solution Approach 1:
The chip guard patterns and buffer slits are merged into a single integrated structure formed through coordinated patterning processes, allowing both stress relief features to be created in conjunction with each other rather than as separate manufacturing steps
Data Source
AI summary
The present technology relates to a memory device and a method of manufacturing the same. A memory device according to an embodiment of the present disclosure includes a main chip region, a chip guard region disposed adjacent to the main chip region, a plurality of chip guard patterns formed in the chip guard region, and a buffer slit formed in a space between the plurality of chip guard patterns.