Memory Chip Security Verification via Controller Universality
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of security functions into memory chips increases costs due to the need for additional circuitry, posing a challenge in providing secure memory devices without excessive cost escalation.
Innovation Solution
A memory device configuration that includes two memory chips, where one chip is coupled to a host controller and equipped with a security unit and address configuration unit, enabling encryption and decryption of data across both chips, thereby providing security without the need for excessive additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If security function is added to memory chip, then data security is improved, but manufacturing cost increases
Solution Approach 1:
The memory controller is designed to perform both traditional memory control functions and security verification functions. The controller includes a verification unit that can verify security parameters of memory chips, and the same controller also manages normal read/write operations. This multi-functionality eliminates the need for separate dedicated security verification hardware, thereby reducing manufacturing costs while maintaining data security.
2Reliability
If security verification mechanism is integrated into memory chip, then security reliability is improved, but device complexity increases
Solution Approach 1:
The security verification unit is merged with the existing memory controller structure rather than being implemented as a separate independent component. The verification unit shares the same physical interface and control logic resources with the normal memory control unit. This merging approach reduces overall device complexity by eliminating redundant circuits while still providing comprehensive security verification capabilities for multiple memory chips.
Data Source
AI summary
A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.