3D Memory Chip Stack Layout for Low-Parasitic Signal Identification
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Solution Overview
Problem
Three-dimensional semiconductor devices face challenges such as large parasitic capacitance and resistance in connection structures between stacked chips, affecting signal transmission quality.
Innovation Solution
A memory chip and logic chip design with symmetrically arranged transmission structures, allowing for efficient signal identification and positioning within a chip stack structure, reducing parasitic capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are stacked to form a three-dimensional semiconductor device, then production cost per unit memory cell is reduced, but parasitic capacitance and resistance in connection structures increase
Solution Approach 1:
The connection structure between stacked chips is segmented into multiple independent transmission lines (first transmission lines and second transmission lines) with distinct functions. The first transmission lines transmit identification signals for chip positioning, while the second transmission lines transmit data signals. This segmentation allows each transmission line to be optimized independently, reducing parasitic effects on each line while maintaining overall system performance.
Solution Approach 2:
The patent introduces intermediate structures including shielding layers and isolation structures between transmission lines. These intermediary elements act as mediators to reduce electromagnetic interference and parasitic coupling between adjacent transmission lines, thereby reducing parasitic capacitance and resistance without compromising the stacking architecture.
2Adaptability or versatility
If connection structures are added between stacked chips, then three-dimensional device functionality is achieved, but signal transmission quality deteriorates due to parasitic effects
Solution Approach 1:
Different regions of the connection structure are assigned different qualities and functions. The first transmission lines are optimized for identification signal transmission with specific impedance characteristics, while the second transmission lines are optimized for data signal transmission. Shielding structures are strategically placed in specific locations to provide localized protection against parasitic effects, improving signal transmission quality in critical areas.
Solution Approach 2:
The patent utilizes the vertical dimension in the stacked chip architecture to arrange transmission lines at different heights and positions. By distributing transmission lines across multiple vertical layers and using through-silicon vias (TSVs) for vertical interconnection, the design reduces parasitic effects by increasing spatial separation while maintaining compact three-dimensional functionality.
Data Source
AI summary
Provided are a memory chip, a logic chip, a chip stack structure, and a memory. In the memory chip, four first transmission structures are arranged symmetrically about a first axis and a second axis; four second transmission structures in each second transmission structure group are arranged symmetrically about the first axis and the second axis; the memory chip receives one first identification signal from each one of the first transmission structures and generates a chip position identification code based on four first identification signals; the memory chip receives one second identification signal from each second transmission structure group and generates a stack position identification code based on B second identification signals.