Memory Chip Test Interface for Contact Impedance Compensation
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Solution Overview
Problem
The issue of contact impedance between a test tool and a device under test (DUT) causes voltage drop, leading to reduced test accuracy, increased test cost, and decreased yield in memory testing, especially for memory products with smaller signal margins.
Innovation Solution
A chip test system and method that compensates for voltage drop by using multiple signal transmission paths with different contact impedances, employing a programmable power supply to adjust test voltage values based on monitor voltages, and utilizing a feedback loop to ensure target voltage values are achieved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the cleaning frequency of the probe is increased to reduce contact impedance, then test accuracy is improved, but service life of the probe is reduced and test cost increases
Solution Approach 1:
The signal transmission path is segmented into multiple parallel paths between the probe and pad, distributing the contact impedance across multiple paths. This reduces the overall impact of contact impedance on test accuracy without requiring increased cleaning frequency, thereby preserving probe service life.
Solution Approach 2:
The system dynamically adjusts test parameters (such as test voltage and current levels) based on real-time contact impedance measurements. By changing these parameters adaptively, the system maintains test accuracy despite varying contact conditions, eliminating the need for frequent probe cleaning.
2Measurement precision
If the cleaning frequency of the probe is increased to reduce contact impedance, then test accuracy is improved, but test time increases
Solution Approach 1:
Multiple parallel signal paths are implemented, allowing the system to maintain accurate measurements without frequent probe cleaning. This eliminates time losses associated with repeated cleaning operations while preserving test accuracy.
Solution Approach 2:
The system incorporates real-time monitoring of contact impedance and automatically adjusts test parameters based on feedback. This continuous adaptation maintains test accuracy without requiring periodic probe cleaning, thereby reducing test time losses.
3Measurement precision
If the cleaning frequency of the probe is increased to reduce contact impedance, then test accuracy is improved, but test cost significantly increases
Solution Approach 1:
The patent implements multiple parallel signal transmission paths, which reduces contact impedance effects without requiring frequent expensive probe cleaning operations. This structural solution maintains test accuracy while significantly reducing test cost.
Solution Approach 2:
The system performs self-adjustment by automatically compensating for contact impedance effects through real-time monitoring and parameter adjustment. This self-service capability eliminates the need for frequent manual probe cleaning, reducing both labor costs and probe replacement expenses.
4Measurement precision
If multiple signal transmission paths are used to reduce contact impedance impact, then test accuracy is improved, but device complexity increases
Solution Approach 1:
The test interface is segmented into multiple parallel signal paths, distributing the measurement function across several paths. While this increases structural complexity, it significantly reduces contact impedance effects and improves test accuracy for memory testing.
Solution Approach 2:
The multiple signal paths serve dual functions: they provide redundant measurement paths to reduce contact impedance effects, and they enable the system to maintain compatibility with existing test architectures, thereby managing complexity while improving accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system maintains test accuracy and reduces test cost by compensating for voltage drops due to contact impedance, thereby improving yield and productivity.
Implementation Method 1
transmit the test signal to the power pad of the memory chip through the first signal transmission path, obtain a monitor voltage generated by the driver pad through the second signal transmission path, and adjust a test voltage value of the test signal by controlling the programmable power supply according to the monitor voltage, the first contact impedance, and the test signal
Implementation Method 2
The test interface is coupled between the memory chip and the test device to provide multiple signal transmission paths. The signal transmission paths include a first signal transmission path having first contact impedance, and a second signal transmission path having second contact impedance
Data Source
AI summary
A chip test system and method are provided. The chip test system includes a memory chip, a test device, and a test interface. The memory chip has a power pad and a driver pad coupled to the power pad. The test device is configured to provide a test signal. The test interface is configured to provide multiple signal transmission paths. The test device transmits the test signal to the power pad of the memory chip through the test interface, obtains a monitor voltage generated by the driver pad, and adjusts a test voltage value of the test signal according to the monitor voltage. The test device comprises a precise measurement unit configured to measure the monitor voltage, and a switch element coupled to the precise measurement unit, and when the memory chip starts to be tested, the switch element is turned on.