Memory Chip Testing via Serial Bus Interface
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices lack a straightforward method to directly access and test memory chips packaged within a Multi-Chip Package (MCP), relying on complex logic chip interactions or costly test pin methods.
Innovation Solution
Incorporating a memory chip testing circuit and a serial bus interface circuit within the memory chip, enabling direct access and testing via an existing standard serial bus, such as I2C, without the need for additional test pins or buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a logic chip is used to access and test the memory chip in an MCP package, then the memory chip can be tested, but the testing method becomes complex and indirect
Solution Approach 1:
The patent introduces a serial bus interface circuit as an intermediary component within the memory chip that enables direct communication between external testing devices and the memory chip through a standard serial bus. This intermediary mechanism eliminates the need for complex logic chip-mediated testing, providing a straightforward testing path while maintaining reliability.
Solution Approach 2:
The memory chip is equipped with a universal serial bus interface that can serve multiple functions: normal data communication and dedicated testing operations. This multi-functionality allows the same interface to be used for both operational purposes and testing purposes, simplifying the testing methodology without requiring separate specialized interfaces.
2Ease of operation
If additional test pins or buses are added to the package for direct memory chip access, then direct testing becomes possible, but design complexity and costs increase
Solution Approach 1:
The patent utilizes an existing standard serial bus interface within the memory chip for dual purposes: normal operational communication and dedicated testing access. This approach enables direct memory chip access without requiring additional test pins or buses, thereby maintaining ease of operation while avoiding increased design complexity.
Solution Approach 2:
The memory chip is designed with self-service capabilities by incorporating an internal serial bus interface that can be directly accessed for testing purposes. This self-contained interface eliminates the need for external testing infrastructure modifications, allowing the memory chip to serve its own testing needs without adding package complexity.
Data Source
AI summary
A semiconductor device is provided where it is possible to access and test a memory chip by a simple method. The semiconductor device that mounts a plurality of chips in a common package includes a logic chip having a predetermined function and a memory chip that is coupled with the logic chip and stores data. The memory chip includes a memory chip testing circuit that performs an operation test of the memory chip and a serial bus interface circuit for transmitting and receiving data between the memory chip testing circuit and a serial bus provided outside the package.