Memory Chip Testing via Parallel Pattern Generation
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Solution Overview
Problem
Existing chip testing methods have limited diversity and test coverage, resulting in insufficient efficiency due to the inability to input multiple test patterns simultaneously, which prolongs the testing time for memory chips.
Innovation Solution
A device and method utilizing a pattern generator to write logic voltages to multiple banks of a memory chip, with opposite voltages applied to other banks, followed by reading and executing logic operations to generate results, allowing for various test patterns and reducing testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple test patterns are input simultaneously to increase testing efficiency, then testing time is reduced, but the complexity of the testing device increases
Solution Approach 1:
The testing device is segmented into multiple independent pattern generators (PG0-PG3), each capable of generating test patterns independently. This segmentation allows parallel operation of multiple test patterns while maintaining manageable complexity through modular design, where each generator handles a specific portion of the testing task.
Solution Approach 2:
Each pattern generator is designed with multi-functionality to generate different test patterns (e.g., D0, D1, D2, D3 patterns) and can operate in different modes (single-mode or dual-mode). This universality allows the same hardware structure to perform multiple testing functions, increasing efficiency without proportionally increasing device complexity.
2Device complexity
If only one or two test patterns are input at a time, then the device complexity remains low, but the test coverage is insufficient
Solution Approach 1:
The testing system transitions from sequential single-pattern testing to parallel multi-pattern testing by adding a temporal dimension. Multiple test patterns are applied simultaneously across different banks (BK0-BK3) in different time slots or concurrently, expanding the testing dimension from one pattern at a time to multiple patterns in parallel, thereby improving test coverage without excessive complexity increase.
3Ease of operation
If logic voltages are written to all banks simultaneously with the same pattern, then testing is simplified, but pattern diversity is reduced
Solution Approach 1:
Different logic voltage patterns (D0, D1, D2, D3) are applied to different banks (BK0, BK1, BK2, BK3) according to specific quality requirements. Each bank receives appropriately tailored test patterns based on its testing needs, allowing simultaneous operation with diverse patterns while maintaining operational simplicity through standardized control logic.
Data Source
AI summary
A device for increasing chip testing efficiency includes a pattern generator, a reading unit, a logic operation circuit, and a judgment unit. The pattern generator is used for writing a logic voltage to each bank of a memory chip. The reading unit is used for reading logic voltages stored in all memory cells of each bank. The logic operation circuit is used for executing a first logic operation on the logic voltages stored in all memory cells of each bank to generate a plurality of first logic operation results corresponding to each bank, and executing a second logic operation on the plurality of first logic operation results to generate a second logic operation result corresponding to the memory chip. The judgment unit determines whether the memory chip passes the test according to the second logic operation result.