Memory Chip Segmentation for High-Resistance, Low-Mobility TFTs
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Solution Overview
Problem
Thin film transistors (TFTs) in memory devices exhibit high resistances, low mobility, and poor uniformity, making them unsuitable for designing amplifiers and memory circuit structures.
Innovation Solution
A memory chip design incorporating a first encoding device generating word line signals and a memory device with synchronized first and second memory circuits, controlled by enabling signals and pulse signals to optimize data signal generation, reducing resistance and current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thin film transistors (TFTs) are used in memory devices, then manufacturing cost is reduced, but resistance increases and mobility decreases
Solution Approach 1:
The memory device is divided into multiple memory circuits (first memory circuit, second memory circuit, etc.) that operate at different nodes and time periods. This segmentation allows each circuit to be optimized independently while using TFTs, mitigating the reliability issues of individual TFTs through system-level architecture.
2Productivity
If multiple memory circuits operate simultaneously, then data processing speed increases, but current consumption increases
Solution Approach 1:
Multiple memory circuits operate periodically rather than simultaneously. The first memory circuit operates during a first time period, then a second memory circuit operates during a second time period, and so on. This periodic operation maintains high data processing throughput while significantly reducing peak current consumption compared to simultaneous operation of all circuits.
3Quantity of substance
If memory circuits are expanded to increase capacity, then storage capacity increases, but device area increases
Solution Approach 1:
Multiple memory circuits share common bit lines and control signals, effectively adding a time dimension to the memory architecture. Instead of expanding only in spatial dimensions (more rows and columns), the system uses multiple circuits operating at different time periods to achieve increased capacity while maintaining compact area.
4Reliability
If TFT uniformity is improved, then amplifier design becomes feasible, but manufacturing complexity increases
Solution Approach 1:
Different memory circuits are positioned at different nodes (first node, second node, etc.) and operate at different time periods, creating local operational zones. This allows each circuit to be optimized for its specific location and function, achieving effective uniformity through distributed architecture rather than requiring uniform improvement across all TFTs, thus avoiding increased manufacturing complexity.
Data Source
AI summary
A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.