Stacked Memory Chip Bonding Layout for Stable Voltage Paths
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently stacking memory chips while maintaining a stable voltage supply and minimizing the chip's area, leading to potential voltage instability and increased size due to complex wiring configurations.
Innovation Solution
The proposed solution involves stacking memory chips with pads on two adjacent sides, connected by bonding wires that extend in a single direction, allowing for a low-resistance voltage path and reducing the need for wide wiring, which minimizes the chip's area and stabilizes voltage supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory chips are stacked with complex wiring configurations to maintain stable voltage supply, then voltage stability is improved, but chip area increases
Solution Approach 1:
The invention segments the voltage supply path by providing separate voltage supply lines for each memory chip in the stack. Each memory chip has its own dedicated voltage supply connection, which eliminates the need for complex inter-chip wiring and reduces the overall chip area while maintaining stable voltage supply to each individual chip.
Solution Approach 2:
The invention transitions from planar wiring configurations to three-dimensional vertical stacking with simplified connections. By stacking memory chips vertically and providing voltage supply through the stack structure, the design reduces the horizontal wiring complexity and minimizes chip area while ensuring stable voltage delivery to all planes.
2Reliability
If wide wiring is used to reduce resistance and stabilize voltage supply, then voltage stability is improved, but chip area increases
Solution Approach 1:
The voltage supply is segmented into multiple independent paths, with each memory chip having its own dedicated voltage supply line. This segmentation allows for optimized current distribution without requiring excessively wide wiring, as each line serves a specific chip and the total wiring area is distributed efficiently throughout the stack structure.
3Adaptability or versatility
If bonding wires are extended in multiple directions to connect stacked memory chips, then connectivity is improved, but device complexity increases
Solution Approach 1:
The invention adopts vertical stacking in the third dimension with bonding wires extending primarily in one direction (vertically between stacked chips). This dimensional transition simplifies the wiring configuration compared to planar multi-directional connections, as the vertical stack architecture naturally organizes connections and reduces the number of wiring directions required to achieve full connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables stable voltage supply to all planes while minimizing the memory chip's area, preventing voltage drop and reducing the chip's size, thereby improving the efficiency and stability of the memory device.
Implementation Method 1
first, second, and third bonding wires... The first bonding wire connects the first pad and the third pad. The second bonding wire connects the fourth pad and the sixth pad. The third bonding wire connects the second pad and the fifth pad.
Data Source
AI summary
A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.