Memory Chip Wait Pad for Die Boundary Crossing Detection
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Solution Overview
Problem
Existing memory devices lack an effective method to detect die boundary crossing operations between stacked memory chips, which is crucial for efficient switching and operation mode management.
Innovation Solution
A memory device comprising two memory chips with a control unit, wait controller, and wait receiver, where the wait controller changes the state of a wait signal at a wait pad to indicate mode changes, allowing detection of die boundary crossing operations and enabling seamless switching between active and inactive modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two memory chips are stacked to form a memory device, then the storage capacity is increased, but the ability to detect die boundary crossing operations is lost
Solution Approach 1:
The patent introduces a wait pad as an intermediary signaling mechanism between stacked memory chips. The wait pad transmits wait signals that indicate when a die boundary crossing operation is occurring, allowing the system to detect and manage transitions between chips without direct communication between the chips themselves.
Solution Approach 2:
The system implements feedback through the wait controller and wait receiver that monitor the wait pad signal state. When a wait signal is detected, the system responds by managing the switching between active and inactive modes, creating a closed-loop feedback mechanism that enables detection and response to die boundary crossing operations.
2Productivity
If boundary crossing operation is performed between stacked memory chips, then the reading/writing operation continuity is improved, but the detection and management of operation mode switching becomes complex
Solution Approach 1:
The wait pad serves as a mediator that simplifies the complexity of inter-chip communication. Instead of complex direct signaling between stacked chips, the wait pad provides a standardized interface that automatically indicates when boundary crossing operations are in progress, reducing the management complexity.
Solution Approach 2:
The memory chips automatically manage their own operation mode switching based on the wait signal detected from the wait pad. The system performs self-service by autonomously transitioning between active and inactive modes without requiring external control, thereby maintaining operational continuity while simplifying management.
3Measurement precision
If wait signal monitoring is implemented on wait pad, then the detection of die boundary crossing operations is enabled, but the device complexity increases
Solution Approach 1:
The wait controller and wait receiver implement a simplified copying mechanism where the wait signal state is monitored and replicated as control information. This allows precise detection of die boundary crossing operations by creating a copy of the wait signal state that can be processed without adding significant complexity to the overall system.
Data Source
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AI summary
A memory chip (10,11) is provided and includes a control unit (100,110), a wait controller (101,111), and a wait receiver (102,112). When the memory chip (10,11) operates in an active mode and the control unit (100,110) determines that the memory chip (10,11) will be changed to operate in an inactive mode according to an input address signal, the wait controller (101,111) changes a state of a wait signal (Sw) at a wait pad (Pw) from a de-asserted state to an asserted state. When the memory chip (10,11) operates in an inactive mode and the wait receiver (102,112) detects that the state of the wait signal (Sw) has been changed from the de-asserted state to the asserted state, the control unit (100,110) determines whether the memory chip (10,11) will be changed to operate in the active mode or a word-line boundary crossing operation will be performed to another memory chip (10,11).