Memory Chip Wait Signal Detection for Die Boundary Crossing
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Solution Overview
Problem
Existing memory devices lack an effective method to detect die boundary crossing operations between stacked memory chips, which is crucial for managing the active and inactive modes of memory chips during reading/writing operations.
Innovation Solution
A memory chip design incorporating a control unit, a wait controller, and a wait receiver that monitors a wait pad to detect state changes, enabling the detection of die boundary crossing operations by altering the wait signal state and determining operation mode changes based on input address and command signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are stacked to form a memory device, then the storage capacity is improved, but the ability to detect boundary crossing operations between chips deteriorates
Solution Approach 1:
The patent introduces a wait signal as an intermediary carrier to transmit boundary crossing operation information between stacked memory chips. The wait signal acts as a mediator that conveys status information from one chip to another, enabling detection without direct complex communication circuits between chips
Solution Approach 2:
The wait pad, originally designed for single-chip wait status indication, is extended to serve multiple functions: it can detect both intra-chip boundary crossings and inter-chip boundary crossings. This multi-functional use allows the same hardware structure to handle different detection scenarios
2Measurement precision
If a wait signal is used to indicate boundary crossing operations, then the status monitoring capability is improved, but the complexity of control logic increases
Solution Approach 1:
The memory chip automatically generates and manages the wait signal based on its own operational state. The control logic internally determines when to assert or de-assert the wait signal based on address signal analysis, eliminating the need for external control circuits or additional signaling mechanisms
3Difficulty of detecting and measuring
If the wait signal state is changed to indicate operation mode transitions, then the detectability of boundary crossing operations is improved, but the risk of signal misinterpretation increases
Solution Approach 1:
The patent implements a feedback mechanism where the wait signal state changes are directly tied to the internal operational state of the memory chip. The control logic continuously monitors address signals and相应ly adjusts the wait signal, creating a reliable feedback loop that prevents misinterpretation
Solution Approach 2:
The control logic analyzes address signals in advance to determine upcoming operation mode transitions before they occur. By proactively setting the wait signal state based on predicted transitions, the system avoids ambiguity and ensures correct signal interpretation
Data Source
AI summary
A memory chip is provided and includes a control unit, a wait controller, and a wait receiver. When the memory chip operates in an active mode and the control unit determines that the memory chip will be changed to operate in an inactive mode according to an input address signal, the wait controller changes a state of a wait signal at a wait pad from a de-asserted state to an asserted state. When the memory chip operates in an inactive mode and the wait receiver detects that the state of the wait signal has been changed from the de-asserted state to the asserted state, the control unit determines whether the memory chip will be changed to operate in the active mode or a word-line boundary crossing operation will be performed to another memory chip.