Memory Chip Test Circuit for Pre-Bonding Yield Screening
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Solution Overview
Problem
The challenge in developing high-capacity and highly-integrated memory devices with three-dimensional memory cell arrays is the need to improve yield by ensuring that only functional memory chips are bonded with peripheral circuit chips.
Innovation Solution
Incorporating a test circuit in the memory chip that performs a test process on the memory cell array before bonding with the peripheral circuit chip, ensuring only functional memory chips are bonded, thereby improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test circuit is added to the memory chip to perform testing before bonding, then the yield is improved, but the device complexity increases
Solution Approach 1:
The test circuit performs a test process on the memory cell array before the memory chip is bonded to the peripheral circuit chip. This preliminary testing action identifies functional memory chips in advance, ensuring that only tested chips proceed to bonding, thereby improving yield while managing complexity through staged testing.
Solution Approach 2:
The test circuit is integrated into the memory chip structure and shares the same substrate and interlayer insulating layers as the memory cell array. This multi-functional integration allows the test circuit to coexist with the memory functionality without requiring completely separate testing equipment or processes, thus improving yield while limiting the increase in device complexity.
2Manufacturing precision
If the memory chip is tested before bonding, then the manufacturing precision is improved, but the productivity decreases due to additional testing time
Solution Approach 1:
The test process is performed on the memory chip before bonding to the peripheral circuit chip. This preliminary testing ensures that only functional chips are selected for bonding, improving manufacturing precision by identifying defective chips early. The bit line connection line extending from the cell array region to the test circuit region enables this pre-bonding test without requiring additional post-bonding testing steps.
Solution Approach 2:
The test circuit is merged with the memory chip structure on the same substrate, sharing interlayer insulating layers and using the same bonding metal patterns for both testing and final connection. This integration allows the test process to be performed using the same fabrication infrastructure, reducing the impact on productivity despite the added testing step.
3Measurement precision
If the bit line connection line extends from the cell array region to the test circuit region, then the test capability is improved, but the area of the memory chip increases
Solution Approach 1:
The bit line connection line is strategically routed to extend from the cell array placement region to the test circuit region, providing localized testing capability where needed. This targeted connection approach enables test capability improvement by establishing electrical pathways only in the specific regions required for testing, rather than adding comprehensive interconnections across the entire chip, thus limiting the area increase.
Solution Approach 2:
The bit line connection line utilizes the vertical dimension by extending through multiple interlayer insulating layers to connect the cell array region to the test circuit region. This three-dimensional routing approach allows test capability improvement without proportionally increasing the planar area of the memory chip, as the connection leverages the vertical stacking architecture already present in the device.
Data Source
AI summary
A memory device which including a memory chip that includes a memory cell array connected to word lines and bit lines, a test circuit connected to the word lines and the bit lines, and a first bonding metal pattern connected to the word lines and the bit lines, and a peripheral circuit chip that includes a peripheral circuit and a second bonding metal pattern. The test circuit performs a test process on the memory cell array, and the memory chip and the peripheral circuit chip are connected in a bonding method for electrically connecting the first bonding metal pattern and the second bonding metal pattern.