Memory Chiplet Bonding for Higher-Yield Control Wafer Assembly

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Solution Overview

Problem

The high failure rates of integrated memory assemblies due to defects in either memory or control dies in bonded wafers, leading to inefficient use of non-defective dies and increased costs in manufacturing.

Innovation Solution

The implementation of die-to-wafer bonding, where memory chiplets are individually bonded to a control circuit wafer, allowing for selective use of non-defective memory dies and enabling configurability through the use of identical or differently configured chiplets, with testing prior to bonding to ensure only non-defective chiplets are used.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If wafer-to-wafer bonding is used to bond multiple non-volatile memory dies to control dies, then integration is achieved, but failure rates increase and yield decreases

Engineering Contradiction:

Improveintegration processVSAvoidassembly failure rate

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the bonding process into two distinct stages: first bonding memory dies to a first wafer, then bonding control dies to a second wafer, and finally bonding the two wafers together. This segmentation allows independent optimization and testing of each bonding interface, reducing the propagation of defects and improving overall assembly reliability while maintaining manufacturing integration.

Inventive Principle:

Principle #1Segmentation

2Ease of manufacture

If a defect in either memory die or control die results in a failed integrated memory assembly, then bonding is achieved, but yield loss increases

Engineering Contradiction:

Improvebonding processVSAvoidmanufacturing yield

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent performs preliminary testing and characterization of memory dies and control dies before bonding, and includes intermediate testing after the first bonding stage. This preliminary action identifies defective components early, allowing them to be replaced before final assembly, thereby reducing yield loss while maintaining the bonding manufacturing process.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If multiple dies are bonded together to form integrated memory assemblies, then functionality is achieved, but the number of defective assemblies increases

Engineering Contradiction:

Improveintegrated functionalityVSAvoidassembly defect rate

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms through multiple testing stages: pre-bonding testing of individual dies, post-bonding testing after the first wafer bonding stage, and final testing after control die bonding. This feedback loop identifies defects at each stage, allowing for corrective actions and component replacement, thereby maintaining high integrated functionality while reducing the defect rate in final assemblies.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20250323231A1Adaptable memory system with multiple chiplets

Publication Date: 2025.10.16 SANDISK TECHNOLOGIES LLC

AI summary

An apparatus includes a silicon wafer and a plurality of memory dies. The silicon wafer includes a plurality of control dies, each control die having first bond pads on a first surface. The plurality of memory dies each have second bond pads on a second surface facing the first surface of the control die. The second bond pads of each memory die are bonded to corresponding first bond pads on the first surface of the memory control circuit.