Memory Chiplet Base-Die Link Mapping for D2D Scalability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scalability and cost-effectiveness of high-bandwidth memory (HBM) chiplets are limited by the edge size of system-on-chip (SoC) compute die, which constrains the number of HBM interfaces, and replacing the HBM physical layer with die-to-die (D2D) interconnects introduces timing issues.
Innovation Solution
Implementing a memory controller in the base die with a link layer that maps between memory controller protocols and D2D interconnect protocols, such as UCIe, and using a multiplexer to switch between link layers for different chiplet types, enabling scalable and power-efficient connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If HBM PHY is replaced with D2D interconnect to improve scalability and adaptability, then scalability and adaptability are improved, but timing issues arise when data is read directly from memory stack to D2D interconnect
Solution Approach 1:
A buffer is introduced as an intermediary component between the memory stack and the D2D interconnect. The buffer temporarily stores data read from the memory stack, allowing the D2D interconnect to operate at its own speed without being constrained by memory read timing. This mediator resolves the timing mismatch between the two components while maintaining data integrity and enabling scalable architecture.
2Adaptability or versatility
If multiple link layers are included to support different chiplet types, then adaptability is improved, but device complexity increases
Solution Approach 1:
A multiplexer is implemented to dynamically select between different link layers based on the type of chiplet being connected. Instead of having all link layers actively present simultaneously, the multiplexer enables only the appropriate link layer for the current connection requirement. This dynamic switching approach maintains adaptability for multiple chiplet types while reducing the effective complexity at any given moment.
Solution Approach 2:
The unnecessary link layers are effectively extracted or removed from the active data path through the use of multiplexer switching. When a specific chiplet type is connected, only the corresponding link layer remains in the signal path, while other link layers are taken out of the active configuration. This reduces the operational complexity while preserving the capability to support multiple chiplet types when needed.
Data Source
AI summary
A system and a method are disclosed for improving memory chiplets. In an embodiment, a memory chiplet comprises a memory stack and a base die. The base die includes a thru-silicon via (TSV) coupled to the memory stack, a memory controller coupled to the TSV through a first interface, and a die-to-die (D2D) interconnect. The base die further includes a link layer coupled to the memory controller configured to map a bus interface from the memory controller to a D2D interface of the D2D interconnect. Data mapped by the link layer is transmitted to a second chiplet with a parallel link layer corresponding to the link layer.