Memory Chiplet With Shared Data Bus for Lower-Latency 3D Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 3-dimensional memory devices face challenges with latency in data transfer between different memory arrays, limiting bandwidth performance in applications requiring fast and high-bandwidth memory access, such as neuromorphic computing and machine learning.
Innovation Solution
A memory structure is designed with multiple memory arrays formed on a single die, including an SRAM array at the semiconductor material level, a DRAM or 1T1C array above the SRAM, and a 3-dimensional FRAM array above the DRAM, connected by a data bus for efficient data transfer, with peripheral control devices located below the arrays to reduce area and shorten connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory arrays are stacked vertically in 3-dimensional devices, then integration density and bandwidth are improved, but latency in data transfer between arrays increases
Solution Approach 1:
The patent transitions from traditional horizontal memory array layouts to a vertical stacking architecture where multiple memory arrays (DRAM, FRAM, MRAM) are arranged in three-dimensional layers. This dimensional change enables higher integration density and bandwidth while the patent simultaneously addresses latency through optimized interconnect design and peripheral control placement.
Solution Approach 2:
The patent introduces a data bus as an intermediary component that spans across all vertically stacked memory arrays, enabling efficient data transfer between layers. Additionally, peripheral control devices are positioned at the periphery to mediate access operations, reducing the distance data must travel and thereby minimizing latency while maintaining high bandwidth.
2Speed
If chips are stacked over chips in 3-dimensional devices, then interconnect length is decreased and speed is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory system into distinct functional segments - different types of memory arrays (DRAM, FRAM, MRAM) are separated into individual stacked layers, each optimized for specific functions. This segmentation allows for modular fabrication and assembly, reducing overall device complexity while maintaining high speed performance through short interconnects within each segment.
Solution Approach 2:
The vertical stack architecture serves multiple functions simultaneously: it provides high-speed memory access through short interconnects, achieves high integration density, and enables diverse memory types to coexist in a single package. The peripheral control devices provide universal access control for all memory arrays, simplifying the interface while managing the complexity of multiple memory technologies.
3Productivity
If memory arrays are vertically stacked, then integration density is improved, but area occupied by peripheral control devices increases
Solution Approach 1:
The patent extracts the peripheral control devices from the central memory array region and positions them at the periphery of the stacked structure. This extraction allows the control devices to share the vertical space efficiently, minimizing the horizontal area they occupy while maintaining high integration density in the memory arrays.
Solution Approach 2:
The patent implements a nested arrangement where peripheral control devices are positioned at the periphery of the vertically stacked memory arrays, effectively nesting the control functionality within the same vertical envelope as the memory arrays. This nesting maximizes space utilization, allowing high integration density without proportionally increasing the area occupied by control devices.
Data Source
AI summary
A disclosed memory structure includes a first memory region including a first memory array of SRAM memory devices, a second memory region including a second memory array of 1T1C memory devices, and a third memory region including a third memory array of FeFET memory devices. The memory structure further includes at least one data bus laterally extending across the first memory region, the second memory region, and third memory region and configured to provide data transfer among the first memory array, the second memory array, and the third memory array. The memory structure further includes a plurality of peripheral circuit devices formed at a semiconductor material layer of the memory structure, the peripheral circuit devices configured to control the first memory array, the second memory array, and the third memory array. At least one of the second memory array and the third memory array may be a 3-dimensional memory array.