Memory Chips Encrypting Row-Hammer Tracking Addresses

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current semiconductor memory systems face data loss due to leakage currents, particularly in memory cells experiencing row hammering, where frequent activations lead to data degradation, necessitating additional target refresh operations to prevent data loss.

Innovation Solution

A memory system comprising multiple memory chips and a memory controller that track and encrypt row-hammer risk information, allowing for targeted refresh operations by generating and transmitting row-hammer addresses, thereby minimizing circuit area and enhancing security.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If tracking circuits are implemented in each memory chip to monitor row-hammer risk, then row hammering protection is improved, but circuit area increases

Engineering Contradiction:
Improverow hammering protectionVSAvoidtracking circuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the tracking function from individual memory chips and relocates it to the memory controller. Each memory chip only needs to provide tracking information for allocated banks, while the memory controller performs the actual tracking and generates row-hammer addresses. This reduces the circuit area required in each memory chip while maintaining row hammering protection capability at the system level.

Inventive Principle:
Principle #2Taking out (Extraction)

2Ease of operation

If tracking information is transmitted in plaintext, then communication simplicity is improved, but security deteriorates

Engineering Contradiction:
Improvecommunication simplicityVSAvoidsecurity
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent introduces encryption as an intermediary layer between the memory chip and memory controller. Tracking information is encrypted before transmission through the data bus, and the memory controller decrypts it for processing. This maintains the simplicity of the communication interface while adding security through the encryption/decryption intermediary process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11651810B2Memory system and memory module including memory chips sharing channel
Publication Date: 2023.05.16 SK HYNIX INC
  • US11651810B2 patent drawing
  • US11651810B2 patent drawing
  • US11651810B2 patent drawing

AI summary

A memory system includes: a plurality of memory chips each including a plurality of banks and each suitable for generating a tracking address by tracking a row-hammer risk of selected banks among the banks, encrypting the tracking address using an encryption key to output tracking information to a corresponding data bus of a plurality of data buses and performing a target refresh operation according to a row-hammer address transferred through a command/address bus; and a memory controller suitable for collecting the tracking information for the banks transferred through the plurality of data buses to generate and output the row-hammer address to the command/address bus.