Non-Volatile Memory Read Method with Chunk-Based Error Correction

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Solution Overview

Problem

The existing read operations in non-volatile memory devices are bottlenecked by the time-consuming error correction process, which hampers the efficiency of continuous read operations across memory pages.

Innovation Solution

A read method that divides page data into smaller chunk data, performs a fast initial error correction on each chunk, and switches to a more comprehensive error correction if necessary, utilizing separate error correction circuits and an indicating signal to manage data output efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a complex plural-bit error correction operation is applied to a memory device, then the data accuracy is improved, but the time required for each error correction operation becomes unexpectedly long

Engineering Contradiction:
Improvedata accuracyVSAvoiderror correction time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides page data into multiple chunk data units and applies a first error correction operation to each chunk separately. This segmentation allows the error correction process to be performed on smaller data units in parallel or sequence, significantly reducing the total error correction time while maintaining data accuracy through the subsequent second error correction operation on the entire page data.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the read operation is continuously performed on a plurality of memory pages, then the read throughput is improved, but the overall efficiency is hampered by the time spent on error correction operations

Engineering Contradiction:
Improveread throughputVSAvoiderror correction time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent performs a first error correction operation on chunk data before performing the second error correction operation on the entire page data. This preliminary error correction on smaller units reduces the burden on the subsequent full-page error correction, enabling faster processing and allowing continuous read operations across multiple memory pages without being bottlenecked by lengthy error correction processes.

Inventive Principle:
Principle #10Preliminary action

3Speed

If a faster error correction operation is performed on smaller chunk data, then the read speed is improved, but the correction capability may be insufficient for uncorrectable errors

Engineering Contradiction:
Improveread speedVSAvoiderror correction capability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements a two-stage error correction process where the first error correction operation on chunk data is followed by a second error correction operation on the entire page data. This continuous error correction approach ensures that errors missed by the first operation are caught by the second operation, maintaining high reliability while achieving faster read speeds through the initial chunk-level correction.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11468963B2Memory device and read method thereof
Publication Date: 2022.10.11 MACRONIX INTERNATIONAL CO LTD
  • US11468963B2 patent drawing
  • US11468963B2 patent drawing
  • US11468963B2 patent drawing

AI summary

A memory device and a read method thereof are provided. The read method of the memory cell array includes: reading a memory cell array to obtain page data; dividing the page data into a plurality of chunk data; performing a first error correction operation on each of the chunk data in sequence to respectively generate a plurality of first corrected chunk data; performing a second error correction operation on the page data to generate corrected page data; and outputting the corrected chunk data by referring to an indicating signal.