Memory Circuit Dynamic Buffer Control for Low Power
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Solution Overview
Problem
Conventional flash memory input buffers struggle with high-speed signal processing, leading to issues with static current consumption, noise tolerance, and signal distortion, particularly when transitioning between logic levels.
Innovation Solution
A memory circuit design incorporating a data receiving stage, data writing circuit, power supply circuit, data output stage, and a state controller that enables or disables these components based on the chip enable signal, optimizing for low power consumption, low noise, and low distortion by using rail-to-rail input buffers and a finite state machine controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a differential type input buffer is used to process high-speed signals, then signal processing speed is improved, but static current consumption increases
Solution Approach 1:
The patent implements dynamic control of the input buffer by enabling it only during active data reception periods and disabling it during idle periods. The controller activates the input buffer when the chip enable signal is detected and deactivates it when data reception is complete, transforming the static buffer into a dynamically controlled component that consumes power only when necessary for high-speed signal processing.
2Ease of operation
If the input buffer is enabled to process signals, then signal reception capability is improved, but noise sensitivity increases during transition points
Solution Approach 1:
The patent applies preliminary action by detecting the chip enable signal before actual data reception begins. The controller activates the input buffer in advance when the chip enable signal is detected, ensuring the buffer is ready to process incoming signals immediately. This preliminary activation allows the system to maintain proper signal reception capability while controlling noise sensitivity by keeping the buffer enabled only during the necessary time window.
3Reliability
If circuit components remain enabled continuously, then operational readiness is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by controlling the input buffer to operate in periodic cycles rather than continuously. The buffer is activated during active communication periods (when chip enable signal is present) and deactivated during idle periods. This periodic operation maintains operational readiness when needed while significantly reducing average power consumption compared to continuous operation.
Data Source
AI summary
A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.