Memory Circuit Clock Driver ODT Timer Power Reduction
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Solution Overview
Problem
High power consumption in memory circuits during on-die termination (ODT) operation due to continuous toggling of the system clock signal, which is undesirable for memory circuit applications.
Innovation Solution
Implementing a clock driver and ODT timer configuration that stops providing the system clock signal when the memory circuit is not in read mode, aligning the transition edge of the system ODT signal with the root clock signal, and ensuring the system clock signal only toggles during read mode, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the system clock signal continuously toggles during ODT operation to control timing at I/O buffers, then the timing control function is achieved, but the power consumption increases significantly
Solution Approach 1:
The patent extracts the timing control function from the continuous toggling clock signal by introducing a separate ODT timer that generates timing control signals independently. The clock driver stops toggling the system clock signal during non-read modes, and the ODT timer provides the necessary timing control without requiring continuous clock toggling, thus resolving the contradiction between maintaining timing control and reducing power consumption
Solution Approach 2:
The patent implements periodic action by having the clock driver toggle the system clock signal only during read mode when needed, and stop toggling during non-read modes. The ODT timer generates timing signals periodically only when required, rather than continuous toggling, which reduces power consumption while maintaining necessary timing control functionality
2Use of energy by moving object
If the clock driver stops providing the system clock signal during non-read modes, then power consumption is reduced, but the timing control at I/O buffers must be maintained
Solution Approach 1:
The patent introduces the ODT timer as an intermediary component that mediates between the need for timing control and the stopped clock signal. The ODT timer generates ODT timing control signals based on the root clock signal and external ODT signal, providing the necessary timing control to I/O buffers without requiring the system clock signal to be actively toggled, thus resolving the contradiction between power reduction and timing control maintenance
Data Source
AI summary
A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop providing the system clock signal when the memory circuit is not in the read mode. The ODT timer is configured to provide a system ODT signal when the memory circuit is not in the read mode, wherein the transition edge of the system ODT signal is aligned with the transition edge of the root clock signal.