Memory Circuit Simultaneous Column Write Control
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Solution Overview
Problem
Existing memory circuits face inefficiencies in writing data to multiple cells in a single column simultaneously, leading to increased write times and potential write disturb events.
Innovation Solution
A memory circuit configuration that allows for simultaneous writing to multiple cells in a column by controlling voltage combinations across word lines, select lines, and bit lines, avoiding partial selection scenarios that could lead to unpredictable states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data are written to multiple cells in a single column simultaneously using conventional memory circuits, then write bandwidth is increased, but write disturb events are exacerbated
Solution Approach 1:
The memory array is segmented into multiple independent columnar structures, each with its own select lines and bit lines. This segmentation allows simultaneous write operations on multiple columns without interfering with each other, as each column operates independently with isolated control signals.
Solution Approach 2:
Different voltage levels are applied to different select lines and bit lines based on the specific write operation requirements. Each column receives customized voltage combinations tailored to its intended write operation, allowing precise control over which cells are written and preventing unwanted write disturb events in other cells.
2Speed
If conventional memory circuits write to multiple cells in a column simultaneously, then write operation speed is improved, but unpredictable states are generated due to partial selection scenarios
Solution Approach 1:
The patent employs multiple voltage levels (e.g., V0, V1, V2, V3) for select lines and bit lines, where each voltage level has a specific function. By changing voltage parameters dynamically during write operations, the circuit can precisely control cell selection states, avoiding ambiguous partial selection scenarios that lead to unpredictable states.
Solution Approach 2:
The control circuit monitors the states of select lines and bit lines during write operations and adjusts voltage applications accordingly. This feedback mechanism ensures that only fully selected cells undergo write operations, preventing partial selection scenarios from creating unpredictable states.
3Loss of time
If write operations are performed on multiple cells simultaneously in conventional circuits, then overall write time is reduced, but write disturb events increase
Solution Approach 1:
The patent extends the control dimension by introducing multiple independent select lines per column and multiple bit lines, creating a multi-dimensional control space. This allows simultaneous write operations on multiple cells across different rows and columns by applying specific voltage combinations, effectively managing write disturb events while maintaining high write bandwidth.
Solution Approach 2:
Before executing write operations, the control circuit pre-configures the voltage levels on select lines and bit lines to ensure only the intended target cells are fully selected. This preliminary configuration prevents write disturb events by ensuring that cells not intended for writing remain in a safe state before the actual write operation begins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances write operation efficiency by reducing overall write times and minimizing write disturb events, enabling increased write bandwidth.
Implementation Method 1
the dielectric layer includes a ferroelectric material and the device is referred to as a ferroelectric random-access memory (FRAM or FeRAM) cell
Data Source
AI summary
A memory circuit includes a memory array and a control circuit. A first column of the memory array includes a select line, first and second bit lines, a first subset of memory cells coupled to the select line and the first bit line, and a second subset of memory cells coupled to the select line and the second bit line. The control circuit is configured to simultaneously activate each of the select line and the first bit line and, during a period in which the select line and first bit line are simultaneously activated, activate a first plurality of word lines, each word line of the first plurality of word lines being coupled to a memory cell of the first subset of memory cells.