Memory Circuit Copy Row Write Command for Simultaneous Data Writing
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Solution Overview
Problem
Existing memory circuit technologies require significant time to write data to memory cells due to the need for multiple clock signals and active commands, making the process inefficient for writing the same data to multiple word lines.
Innovation Solution
The memory circuit employs a controller that enables a copy row write command to simultaneously write data into memory cells sharing sense amplifiers across multiple bit lines and word lines, reducing the time required for data writing by leveraging shared sense amplifiers to directly copy data between memory cell groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller uses traditional write commands to write data to memory cells corresponding to multiple word lines, then the data can be written into the memory cells, but the writing process requires multiple clock signals and active commands for each word line, resulting in significant time consumption
Solution Approach 1:
The patent merges multiple write operations into a single copy row write command. When the same data needs to be written to multiple word lines, the controller issues one copy row write command that simultaneously copies data from a source row to multiple destination rows, combining what would traditionally require multiple separate write operations into a single unified operation.
Solution Approach 2:
The patent implements a copy row write mechanism where data from a source memory row is copied to multiple destination memory rows in a single operation. The copy row write command enables the controller to replicate data across multiple word lines by leveraging the shared sense amplifier infrastructure, effectively copying data rather than writing it separately to each location.
2Adaptability or versatility
If the controller writes the same data to memory cells corresponding to different word lines using traditional methods, then each word line can be written independently, but the process requires executing the full sequence of active commands and write commands for each word line separately
Solution Approach 1:
The patent combines multiple independent write operations into a single copy row write command that can simultaneously update multiple word lines. The controller merges the sequencing of multiple active commands and write commands into one unified command sequence, maintaining the ability to address individual word lines while executing them in parallel through the copy operation.
Solution Approach 2:
The copy row write command serves multiple functions simultaneously: it writes data to multiple destination word lines, copies data from a source row, and manages the coordination of shared sense amplifiers. This multi-functional command replaces what would traditionally require multiple specialized write commands, improving productivity while maintaining adaptability.
3Quantity of substance
If multiple bit switches are turned on sequentially using M clock signals for writing data, then data can be written to M memory cells, but the writing process takes at least the time of M clock signals plus active command time
Solution Approach 1:
The patent uses a copy row write command that copies data from a source row to multiple destination rows simultaneously, eliminating the need for sequential bit switch activation. Instead of turning on M bit switches one after another using M clock signals, the copy operation leverages the shared sense amplifier to replicate data across multiple word lines in a single operation, dramatically reducing the duration while maintaining the quantity of cells written.
Data Source
AI summary
A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.