Memory Circuit Layout Reducing DQS Signal Path Length
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Solution Overview
Problem
The large tDQS2DQ value in LPDDR4 memory is susceptible to temperature and voltage interferences, leading to performance issues and increased current consumption due to the long transmission path of the DQS signal to the DQ input circuit module.
Innovation Solution
The integrated circuit structure is designed with a smaller circuit region compared to the pad region, reducing the path length for the DQS signal and alleviating temperature and voltage interferences, which improves signal integrity and memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DQS signal is transmitted in advance with a large tDQS2DQ value to compensate for transmission delay, then the data sampling timing can be synchronized, but the transmission path becomes longer and more susceptible to temperature and voltage interferences
Solution Approach 1:
The patent changes the spatial arrangement dimension by making the circuit region size along the target direction smaller than the pad region size. This dimensional optimization shortens the transmission path from pad to circuit module, reducing the tDQS2DQ value and making the transmission path less susceptible to temperature and voltage interferences while maintaining proper signal timing
2Reliability
If the DQS signal is transmitted in advance with a large tDQS2DQ value, then data sampling timing can be synchronized, but the current consumption increases
Solution Approach 1:
The patent changes the timing parameter tDQS2DQ by optimizing the spatial layout. By making the circuit region smaller than the pad region along the target direction, the transmission path length is reduced, which decreases the required advance transmission time and thus reduces current consumption while maintaining data sampling synchronization
3Object-affected harmful factors
If the transmission path length is reduced by making the circuit region smaller than the pad region, then temperature and voltage interferences are reduced, but the layout design becomes more constrained
Solution Approach 1:
The patent applies local quality optimization by specifically designing the circuit region to be smaller than the pad region along the target direction. This localized spatial constraint focuses the optimization on the critical transmission path area, reducing temperature and voltage interferences where they matter most while allowing other areas of the device to maintain standard layout practices
Data Source
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AI summary
The present disclosure provides an integrated circuit structure and a memory, and relates to the field of semiconductor memory technologies. The integrated circuit structure includes: a pad region including a plurality of signal pads arranged along a target direction; and a circuit region arranged on one side of the pad region, and including a plurality of input/output circuit modules arranged along the target direction and correspondingly connected to the signal pads. Each of the input/output circuit modules is configured to implement a sampling operation of an input signal and write a sampling result into a storage array, and read data stored in the storage array. A size of the circuit region along the target direction is less than that of the pad region along the target direction. The performance of a write operation can be improved for the memory in the present disclosure.