Memory Circuit Engine Managing Meta-stability
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Solution Overview
Problem
Conventional STT-MRAM devices lack structures to track write errors and manage power consumption, leading to high write error rates and potential overflow in error tracking mechanisms, and they do not prevent verify operations from occurring close to write operations.
Innovation Solution
A memory device with dynamic redundancy registers, specifically an e1 register and an optional e2 register, that allows for error tracking, re-write operations, and data relocation without impacting throughput or speed, using a pipeline structure to manage write and verify operations transparently and efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error tracking structures are added to STT-MRAM devices, then write error rate management is improved, but device complexity increases
Solution Approach 1:
The patent implements a hierarchical error tracking system where e1 registers are nested within each memory bank to track errors at the bank level, while e2 registers provide overflow handling at a higher level. This nested structure allows comprehensive error tracking without requiring a completely new complex system, as each level builds upon the previous level's functionality.
Solution Approach 2:
The error tracking system is segmented into multiple independent components: e1 registers associated with individual memory banks for primary error tracking, and e2 registers for overflow management. This segmentation allows each component to be optimized independently and reduces the complexity burden on any single structure while collectively providing robust error management.
2Reliability
If dynamic redundancy registers are added for error tracking, then data integrity is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic verification operations where data in the pipeline is verified at specific intervals rather than continuously. The verify register holds data awaiting verification, and verification occurs periodically when resources are available. This periodic action maintains data integrity while avoiding the continuous power consumption that would result from constant verification.
Solution Approach 2:
The error tracking and verification system operates autonomously using available idle cycles and existing memory infrastructure. The system self-manages error tracking without requiring continuous external intervention or additional power-intensive active monitoring, utilizing the memory device's own operational cycles for verification activities.
3Measurement precision
If verify operations are performed immediately after write operations, then data verification is improved, but meta-stability errors increase
Solution Approach 1:
The patent implements a delay mechanism that introduces a predetermined period between write operations and verify operations. The verify register holds data awaiting verification, and the actual verification is postponed until the meta-stability period has elapsed. This preliminary delay action ensures that the magnetic states have stabilized before verification occurs, preventing meta-stability errors while maintaining verification accuracy.
4Reliability
If error buffer capacity is increased to prevent overflow, then error tracking reliability is improved, but device area increases
Solution Approach 1:
The error tracking capacity is segmented across multiple memory banks, with each bank having its own e1 register. This distribution allows the system to track errors from multiple banks simultaneously without requiring a single large centralized error buffer. The segmentation approach maintains high error tracking reliability while minimizing the area required in any single location.
Solution Approach 2:
The patent adds a second dimension to error tracking by implementing e2 registers that handle overflow from e1 registers. Instead of increasing the size of a single error buffer, the system creates a hierarchical structure where e2 registers provide additional tracking capacity in a different organizational dimension. This approach increases error tracking reliability without proportionally increasing device area, as the overflow handling is distributed across multiple banks.
Data Source
AI summary
A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells and a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank. The memory also comprises a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, and wherein a write verification operation associated with a data word of the second plurality of data words is performed a predetermined period of time after the data word is written into the memory.