Memory Circuit Error Detection Outside Data Output Path
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Solution Overview
Problem
Conventional memory circuits with error check and correct circuits experience increased output access time due to the presence of error correction mechanisms in the data output path, and they are not effective enough in reducing the frequency of soft errors caused by cosmic rays and alpha radiation.
Innovation Solution
A memory circuit design that performs error detection and correction outside of the data output path, allowing data to be read without error detection or correction, and periodically checks for errors when not accessed, reducing the occurrence of soft errors and maintaining high-speed access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error check and correct circuit is added to memory circuit, then reliability is improved, but output access time is increased
Solution Approach 1:
The patent performs error detection and correction operations in advance during periods when the memory is not being accessed for normal read/write operations. The error correction section periodically checks stored data and corrects errors before they affect normal operations, allowing fast access during normal operations without error checking overhead.
Solution Approach 2:
The patent implements periodic error detection and correction operations at intervals during non-access periods. The control circuit activates the error correction section only during idle periods or when not responding to external access requests, creating a periodic pattern of error checking that maintains reliability without continuously slowing down access operations.
2Reliability
If error detection is performed during data output, then reliability is improved, but productivity is reduced
Solution Approach 1:
Error detection and correction are performed in advance during idle periods before normal data output operations begin. This preliminary error handling ensures data accuracy is maintained while allowing high-speed output during normal operations without the overhead of real-time error checking.
Solution Approach 2:
The patent separates error detection and correction operations from the normal data output path. Error correction is extracted and performed independently during non-access periods, allowing the main data output path to operate at full speed without being blocked by error checking procedures.
3Productivity
If memory cell area is reduced for microscaling, then productivity is improved, but reliability is worsened
Solution Approach 1:
The memory circuit performs self-diagnosis and self-correction through the integrated error correction section. The system monitors its own stored data for errors and automatically corrects soft errors without external intervention, enabling compact memory cells to maintain high reliability through autonomous error management.
Solution Approach 2:
The error correction section continuously monitors stored data and provides feedback about error conditions. When errors are detected in the compact memory cells, the system activates correction procedures to restore data integrity, creating a feedback loop that maintains reliability despite reduced cell size and increased vulnerability to soft errors.
Data Source
AI summary
A memory circuit includes a data storage section for storing a plurality of data sets and a plurality of redundant data sets, which are used for error correction for the data sets; and an error correction section for performing at least error detection for the data sets in the data storage section by using the redundant data sets when the memory circuit is not accessed from outside for data input or output, and outputting at least result of the error detection as an error detection signal. When the memory circuit is accessed so as to output a designated one of the stored data sets, the designated data set is outputted without being subjected to the error detection by the error correction section.