Memory Circuit Feedback Configuration for Read Speed
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Solution Overview
Problem
Existing memory circuits face challenges in reducing standby power consumption and increasing read operation speed, particularly due to loading issues and variations in drive voltage during read operations.
Innovation Solution
The implementation of a feedback configuration in memory circuits that includes a current path with a resistance-based memory device and a replica resistive device, along with a local buffer circuit to generate a bias voltage used by a voltage clamp device, effectively reduces loading and increases read operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a feedback configuration with replica resistive device is implemented, then read operation speed is increased, but device complexity increases
Solution Approach 1:
A replica resistive device is created as a copy of the memory device under test. This replica device replicates the resistance characteristics and loading effects, allowing the feedback circuit to compensate for voltage drops without requiring complex real-time measurements of the actual memory device during read operations.
Solution Approach 2:
The patent implements a feedback configuration where the voltage drop detected across the replica resistive device is fed back to adjust the drive voltage applied to the memory device. This feedback mechanism dynamically compensates for loading effects and maintains consistent read voltage, thereby increasing read operation speed.
2Speed
If drive voltage is increased to improve read speed, then read operation speed increases, but standby power consumption increases
Solution Approach 1:
The drive voltage is made dynamic rather than static. During read operations, the drive voltage is increased to compensate for loading effects and maintain read speed. During standby periods, the drive voltage is reduced to minimize power consumption. This dynamic adjustment is achieved through the feedback configuration that monitors actual read conditions.
Solution Approach 2:
The patent changes the drive voltage parameter dynamically based on operational state. By detecting the voltage drop across the replica device during reads and adjusting the drive voltage accordingly, the system achieves high read speed when needed while consuming minimal power during standby, effectively decoupling read speed from continuous high power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases standby power consumption, enhances the ability to deliver dynamic charge, and improves the speed of memory circuits by maintaining a consistent drive voltage during read operations.
Implementation Method 1
a resistance-based memory device and a replica resistive device that mimics resistance characteristics of at least a portion of the current path including the resistance-based memory device
Data Source
AI summary
A memory circuit includes an operational amplifier configured to generate a bias voltage at an output terminal responsive to reference and feedback voltages received at respective first and second input terminals, a first NMOS device including a gate coupled to the output terminal of the operational amplifier, a second NMOS device including a gate coupled to a source terminal of the first NMOS device and a source terminal coupled to the second input terminal of the operational amplifier, a resistive device coupled between the source terminal of the second NMOS device and a power reference node, a third NMOS device including a gate coupled to the output terminal of the operational amplifier, a fourth NMOS device including a gate coupled to a source terminal of the third NMOS device, and a resistance-based memory device coupled between a source terminal of the fourth NMOS device and the power reference node.