Memory Circuit Halting Program Counter for Instruction Fetching
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Solution Overview
Problem
The overhead associated with calling subroutines or macros in computer systems, due to the process of storing and retrieving return addresses, consumes multiple clock cycles, leading to performance limitations and slowed operation.
Innovation Solution
A memory circuit configured to store compressed program code, which identifies repeated sequences of instructions, replaces them with unconditional flow control instructions, and manages the flow of program execution to reduce cycle overhead and improve instruction fetching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor stores and retrieves return addresses for subroutine calls, then the program execution can be properly managed, but the operation consumes multiple clock cycles and slows down performance
Solution Approach 1:
The patent extracts the return address management function from the processor and relocates it to the memory circuit. The memory circuit now stores return addresses in dedicated return address storage locations and automatically retrieves them, eliminating the processor's involvement in this overhead-intensive task and thereby improving operation speed while maintaining reliable program execution management
Solution Approach 2:
The patent implements preliminary action by pre-storing return addresses in the memory circuit's return address storage locations before the processor needs them. When a subroutine call occurs, the memory circuit automatically provides the pre-prepared return address, eliminating the time the processor would otherwise spend calculating and storing return addresses, thus improving operation speed without compromising execution management
2Productivity
If the memory circuit decodes unconditional flow control instructions and manages instruction flow, then instruction prefetching efficiency is improved, but the memory circuit complexity increases
Solution Approach 1:
The patent merges the instruction decoding function with the memory circuit's existing instruction storage and retrieval functions. The memory circuit now performs both storage and decoding operations, eliminating the need for separate decoding logic in the processor and improving instruction prefetching efficiency. This consolidation increases memory circuit complexity but reduces overall system complexity and improves performance
Solution Approach 2:
The patent makes the memory circuit multi-functional by enabling it to perform not only instruction storage and retrieval but also instruction decoding and flow control management. This universal function allows the memory circuit to actively participate in instruction processing, improving prefetching efficiency while the increased complexity is offset by the elimination of separate decoding components in the processor
Data Source
AI summary
A memory circuit included in a computer system includes a memory array that stores multiple program instructions included in compressed program code. In response to receiving a fetch instruction from a processor circuit, the memory circuit may retrieve a particular instruction from the memory array. The memory circuit may, in response to a determination that the particular instruction is a particular type of instruction, retrieve additional program instructions from the memory array using an address included in the particular instruction, and send the particular program instruction and the additional program instructions to the processor circuit.