Semiconductor Memory Circuitry for High Density and Low Leakage
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration, reducing manufacturing costs, power consumption, and size while enhancing operation speed.
Innovation Solution
A semiconductor device comprising multiple circuits and transistors with specific functions, including a first circuit connected through various wirings, transistors for establishing electrical continuity, and capacitors for potential changes, integrated in layers with Si and OS transistors, to form a highly integrated and efficient memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory cells are stacked to achieve higher integration density, then integration density is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements three-dimensional stacking of memory cells in the vertical direction (Z-axis) rather than expanding in the planar direction. Multiple memory cell stacks are formed by stacking insulating films, conductive films, and semiconductor layers repeatedly, achieving higher integration density by utilizing the third dimension.
Solution Approach 2:
The memory device is divided into multiple independent memory cell stacks, each containing bit lines, word lines, and storage nodes. These segmented stacks can be manufactured using repeated processing steps, making the complex structure more manageable in terms of fabrication.
2Loss of energy
If conventional semiconductor materials are used, then manufacturing process is well-established, but leakage current is high and power consumption increases
Solution Approach 1:
The patent changes the material parameter by using oxide semiconductor films (such as IGZO - indium gallium zinc oxide) instead of conventional silicon-based semiconductors. This material substitution fundamentally changes the electrical characteristics, enabling extremely low leakage current (10^-21 to 10^-24 A) while maintaining good electrical properties for transistor operation.
3Loss of energy
If oxide semiconductor transistors are used to reduce leakage current, then power consumption is reduced, but transistor performance and operation speed may be compromised
Solution Approach 1:
The patent employs composite material structures where oxide semiconductor films are combined with specific insulating films (such as silicon oxide, silicon nitride) and conductive films. This composite structure optimizes both the low-leakage property of the oxide semiconductor and the electrical performance required for fast operation, achieving a balance between power consumption and speed.
Data Source
AI summary
A novel semiconductor device is provided. A first circuit is electrically connected to a second circuit through a first wiring; the first circuit is electrically connected to a fourth circuit through each of a third wiring and a fourth wiring; the second circuit is electrically connected to a third circuit through a fifth wiring; the first circuit has a function of establishing or breaking electrical continuity among the first wiring, a second wiring, the third wiring, and the fourth wiring; the third circuit has a function of retaining a potential corresponding to first data; the second circuit has a function of supplying the potential corresponding to the first data from the first wiring to the fifth wiring, a function of retaining a potential corresponding to second data, and a function of amplifying a change in a potential of the fifth wiring and outputting the amplified change to the first wiring; and the fourth circuit has a function of outputting the potential corresponding to the first data or the second data in accordance with a potential difference between the third wiring and the fourth wiring.