Memory Circuit Inverts Logic 1s to Reduce CIM Energy
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Solution Overview
Problem
Existing memory circuits for computing-in-memory (CIM) applications face challenges in reducing energy consumption, particularly due to the higher energy requirements of memory cells storing logic 1s compared to logic 0s.
Innovation Solution
The proposed memory circuit configures the memory cell array to store less logic 1s than logic 0s, thereby reducing energy consumption. This is achieved through a memory macro that includes a memory cell array, a multiply-accumulate (MAC) circuit, and an input/output (IO) circuit, which collectively manage the storage and processing of weight signals and inverted weight signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If memory cells store logic 1s, then data representation capability is maintained, but energy consumption increases
Solution Approach 1:
The patent applies local quality by differentiating the treatment of logic 0 and logic 1 values in the weight matrix. Instead of uniformly representing all values, the system selectively inverts only the logic 1 values to logic 0, while keeping logic 0 values unchanged. This localized transformation optimizes energy consumption for specific data patterns without compromising overall data representation capability.
Solution Approach 2:
The patent implements inversion by transforming logic 1 values to logic 0 values in the weight matrix stored in memory cells. This inversion strategy exploits the asymmetric energy consumption characteristics of memory cells, where storing logic 0 requires less energy than storing logic 1. By inverting the conventional representation, the system achieves energy efficiency while maintaining computational correctness through compensating operations in the MAC circuit.
2Use of energy by moving object
If memory cell array stores optimized configuration with fewer logic 1s, then energy consumption is reduced, but circuit complexity increases
Solution Approach 1:
The patent merges the weight matrix storage with the computing function by integrating the MAC (multiply-accumulate) circuit directly with the memory cell array. This combination allows the system to perform computations in-place within the memory structure, eliminating the need for separate storage and processing units. The merged architecture includes dual bit line structures (BL and BLB) that facilitate both storage and computing operations, reducing overall system complexity despite the optimized weight representation.
Data Source
AI summary
A memory circuit includes a memory cell array configured to store a set of stored data, a multiply-accumulate (MAC) circuit and an input output (IO) circuit. The set of stored data is a first set of weight signals or a set of inverted weight signals. The MAC circuit is configured to generate a first set of data in response to a second set of data and the set of stored data. The IO circuit includes a first circuit and a second circuit. The first circuit is configured to send the first set of weight signals in response to a set of enable signals, or generate the set of inverted weight signals in response to a set of inverted enable signals. The second circuit is configured to output a first set of output signals in response to the first set of data and the set of enable signals.