Memory Peripheral Circuit Modes for Lower Read/Write Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices, particularly volatile memory devices like DRAM, face increased power consumption due to higher operation speeds and memory capacities, which is detrimental in battery-powered mobile devices, leading to degraded user experience.
Innovation Solution
A semiconductor memory device with a mode controller that dynamically adjusts its operation mode based on access type, enabling a normal, read-only, or write-only mode to reduce power consumption by disabling unnecessary circuits through clock or power signal gating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operation speed and memory capacity are increased to improve performance, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the memory device's operational state changeable based on access patterns. The mode controller dynamically switches between normal mode and power-saving modes (read-only or write-only modes) depending on whether read or write operations are detected, allowing the system to adapt its power consumption to actual usage requirements while maintaining high performance when needed
2Adaptability or versatility
If all peripheral circuits are enabled to support both read and write operations, then adaptability is improved, but power consumption increases
Solution Approach 1:
The patent segments the peripheral circuits into read-specific circuits and write-specific circuits. The mode controller then selectively enables only the necessary segment based on the access pattern - enabling read circuits in read-only mode, write circuits in write-only mode, or both in normal mode. This segmentation allows the system to maintain full adaptability while reducing standby power by keeping unnecessary circuit segments disabled
Solution Approach 2:
The patent changes the operational parameter of the peripheral circuits from a static 'always-on' state to a dynamic state controlled by the mode controller. By changing the enable/disable parameter of specific circuits based on detected access patterns, the system maintains versatility when needed while minimizing power consumption during extended read or write sequences
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cells, a plurality of peripheral circuits, and a mode controller. The plurality of peripheral circuits perform a write operation for storing write data transmitted from a memory controller into the plurality of memory cells and a read operation for reading out read data of data stored in the plurality of memory cells to transfer the read data to the memory controller. The mode controller is configured to receive mode information from the memory controller, and, based on the mode information from the memory controller, control the plurality of peripheral circuits to operate in one of a normal mode for performing both the write operation and the read operation, a read-only mode for performing the read operation without performing the write operation, or a write-only mode for performing the write operation without performing the read operation.