Memory Circuit With Oxide Semiconductor For Data Retention
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Solution Overview
Problem
Existing memory circuits in signal processing units face challenges in maintaining data integrity and low power consumption, particularly when power is stopped for short durations, as they require complex manufacturing processes and external nonvolatile memory solutions that are inefficient for quick data retrieval.
Innovation Solution
A memory circuit design incorporating a volatile memory section and a nonvolatile memory section with transistors, where a data signal is held in an oxide semiconductor layer capacitor, allowing data retention during power off and resetting to prevent malfunction upon power resumption, using a reset circuit to set the signal potential and reduce transistor degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a nonvolatile memory circuit is located in the periphery of a volatile memory circuit to hold data during power stop, then data retention during power off is improved, but the manufacturing process becomes complicated
Solution Approach 1:
The patent merges volatile and nonvolatile memory functions into a single integrated memory circuit structure. The memory circuit includes a first transistor with an oxide semiconductor layer, a capacitor, and a reset circuit all integrated together, eliminating the need for separate volatile and nonvolatile memory circuits in the periphery. This integration maintains data retention capability while simplifying the manufacturing process.
Solution Approach 2:
The memory circuit is designed to perform multiple functions: it can operate as a volatile memory during normal operation and as a nonvolatile memory during power stop conditions. The oxide semiconductor layer enables the circuit to retain data without continuous power supply, while the reset circuit ensures proper initialization upon power resumption, providing universal memory functionality.
2Use of energy by moving object
If power supply is stopped to achieve low power consumption, then power consumption is reduced, but data loss occurs in volatile memory circuits
Solution Approach 1:
The memory circuit is designed with an oxide semiconductor layer that inherently retains data even when power is stopped. The circuit structure is prepared in advance to maintain data state without power, so when power stop occurs for low power consumption, the data is already in a retainable state due to the oxide semiconductor's properties.
Solution Approach 2:
The oxide semiconductor layer acts as an intermediary between the capacitor and the external environment, maintaining the data state stored in the capacitor during power stop conditions. It mediates the transition between powered and unpowered states, ensuring data integrity without requiring continuous power supply.
3Reliability
If data is held in a capacitor during power stop, then data retention is achieved, but transistor degradation occurs
Solution Approach 1:
The reset circuit monitors the state of the memory circuit and provides feedback control. Upon power resumption, the reset circuit detects the retained data state and performs necessary reset operations to prevent transistor degradation, ensuring both data retention and transistor durability are maintained through active monitoring and control.
Solution Approach 2:
The memory circuit is designed to automatically manage its own state through the reset circuit, which self-regulates the transistor conditions during and after power stop periods. The circuit performs self-diagnosis and self-correction to prevent degradation, reducing the need for external intervention.
4Reliability
If external memory circuit is used to backup data during power stop, then data loss is prevented, but data retrieval time increases
Solution Approach 1:
The nonvolatile memory functionality is nested within the volatile memory circuit structure itself. The oxide semiconductor layer and capacitor are integrated into the same memory circuit, creating a nested structure where the nonvolatile function is contained within the volatile memory architecture, enabling quick data retrieval without external memory access.
Solution Approach 2:
The patent adds a temporal dimension to the memory operation by enabling the same physical circuit to operate in different modes (volatile during power on, nonvolatile during power off). This dimensional change in operational state allows the circuit to provide both fast access and data retention capabilities without requiring separate memory locations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables efficient data retention during power off and quick recovery upon power resumption, reducing power consumption and simplifying manufacturing processes while preventing data loss and transistor degradation.
Implementation Method 1
a transistor whose channel is formed in an oxide semiconductor layer allows a data signal to be held in the capacitor for a long period of time
Implementation Method 2
the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit
Data Source
AI summary
While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit.