Memory Circuit Permutation Network for In-Situ Calculation
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Solution Overview
Problem
Existing memory circuits that perform both data storage and in-situ calculations are limited by their ability to simultaneously process multiple rows, leading to inefficiencies in operations such as permutation and arithmetic operations.
Innovation Solution
A memory circuit design that includes a permutation circuit with a configurable routing architecture, allowing for simultaneous activation of multiple rows and efficient data permutation operations, along with a control circuit that implements calculation and permutation operations by reading configuration data and copying it into registers, and an additional non-volatile memory for storing configuration data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional memory circuit selects only one row at a time during read operations, then the circuit structure is simple, but the productivity for performing calculation operations is reduced
Solution Approach 1:
The control circuit is divided into multiple row decoders, with each decoder responsible for selecting a specific row. This segmentation allows multiple rows to be selected simultaneously for read operations, enabling parallel processing of calculation operations while maintaining manageable complexity in each individual decoder unit.
Solution Approach 2:
The control circuit is designed to perform multiple functions: it can select single rows for conventional read operations, select multiple rows simultaneously for calculation operations, and coordinate with the permutation circuit. This multi-functionality allows the same control circuit to serve both simple memory access and complex calculation operations without requiring separate dedicated circuits.
2Loss of time
If permutation operations are performed using traditional sequential methods, then the device complexity is low, but the time required for permutation operations increases
Solution Approach 1:
The permutation circuit uses a Benes network architecture that transforms the sequential permutation process into a parallel structure by adding spatial dimensions. Multiple permutation operations can be performed simultaneously through the multi-stage switching network, reducing the time complexity from O(N) to O(log²N) while increasing the spatial complexity of the circuit.
Solution Approach 2:
The permutation circuit acts as an intermediary between the memory array and the output, providing a dedicated routing structure that can rearrange data in parallel. This intermediary circuit absorbs the complexity of permutation operations, allowing the rest of the memory system to remain simple while achieving fast permutation through the specialized Benes network.
3Productivity
If multiple rows are simultaneously selected for reading to perform calculation operations, then the productivity is improved, but the control circuit complexity increases
Solution Approach 1:
The row selection control is segmented into multiple independent row decoders, each capable of selecting a specific row. This allows the control circuit to simultaneously activate multiple rows by independently controlling each decoder, enabling parallel read operations for calculation while keeping each decoder unit relatively simple.
Solution Approach 2:
The control circuit prepares the row selection signals in advance by pre-configuring the row decoders before the actual read operation. This preliminary action allows the system to quickly switch between different row selection patterns (single row vs. multiple rows) without adding significant complexity to the core read mechanism.
4Productivity
If the permutation circuit configuration depends on input register contents, then the adaptability is high, but the time for permutation operations becomes variable
Solution Approach 1:
The permutation operation is performed in two stages: first, a content-independent preliminary permutation is applied that can be executed in fixed time; second, if needed, a content-dependent permutation is applied. This preliminary action ensures that the critical path has a fixed time requirement while still allowing adaptability for specific data patterns when necessary.
Solution Approach 2:
The permutation circuit operates in periodic cycles with a fixed duration for the standard Benes network permutation. Additional content-dependent permutations can be inserted in subsequent cycles, allowing the system to maintain a predictable periodic rhythm while still providing adaptability when required by the application.
Data Source
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AI summary
The present description relates to a memory circuit (200) comprising: - a plurality of elementary storage cells (10) arranged in a matrix according to rows and columns, the cells of the same column sharing the same read bit line (RBL) and the same write bit line (WBL); - an internal control circuit (CTRL) adapted to implement a calculation operation comprising the simultaneous activation in read of at least two rows of the matrix; and - a swap circuit (30) comprising a data input register (32), a configuration register (36), and an output port (34), the swap circuit (30) being adapted to provide on its output port (34) the data stored in its input register (32) swapped according to a permutation defined according to the state of its configuration register (36).