Memory Circuit with Segmented Word Lines to Reduce Read Disturbance
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Solution Overview
Problem
Read disturbance in memory cells due to high voltage application during read operations leads to bit state alterations in adjacent cells, causing data errors and requiring block clearing to restore the initial state.
Innovation Solution
A memory circuit design where storage cells are alternately connected to multiple word lines and bit line pairs, allowing simultaneous read/write operations to reduce the disturbance effect and necessary time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied during read operations to access storage states, then read operation can be performed, but read disturbance occurs and alters bit states of adjacent cells
Solution Approach 1:
The patent divides a single word line into multiple segmented word lines (first word line and second word line) that are selectively activated. Instead of activating the entire word line during read operations, only specific segments are activated based on the target cell location, thereby isolating adjacent cells from high voltage exposure and preventing read disturbance while maintaining data accuracy.
2Productivity
If the entire word line is activated for reading, then all storage cells in the row can be accessed, but disturbance to adjacent storage cells increases
Solution Approach 1:
The patent implements local quality by making different segments of the word line have different activation states during read operations. The first and second word line segments are selectively activated or deactivated based on which storage cell is being accessed, ensuring that only the local region containing the target cell experiences high voltage, while other regions remain unaffected, thus maintaining data integrity without sacrificing read speed.
3Reliability
If multiple read/write operations are performed sequentially, then each operation can be completed, but total read/write time increases
Solution Approach 1:
The patent enables continuity of useful action by allowing parallel activation of multiple bit lines (first bit line and second bit line) with their respective word line segments. Multiple read or write operations can be performed simultaneously on different storage cells within the same row, eliminating sequential waiting time and significantly reducing total operation time while maintaining accuracy through selective segment activation.
Data Source
AI summary
A memory circuit, including multiple storage cells arranged in an array with multiple columns and rows, multiple word lines extending in row direction and connecting with the gates of storage cells, multiple bit lines extending in column direction and connecting respectively with the storage cells, wherein the storage cells in each row correspond to m word lines, m is an integer equal or greater than 2, and the m word lines are sequentially and alternately connected with the storage cells in the row. Alternatively, the storage cells of each column correspond to n bit line, n is an integer equal or greater than 2, and the n bit lines are sequentially and alternately connected with the storage cells in the column.