Memory Circuit Power Management via Sub-Array Segmentation
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Solution Overview
Problem
Conventional memory architectures in integrated circuits face challenges in reducing power consumption without increasing size or impacting performance, as they require significant power and area due to the need for multiple memory blocks and associated peripheral circuitry.
Innovation Solution
Implementing a memory circuit with multiple sub-arrays, where only a selected subset is powered at any given time, utilizing shared circuitry to control functions across sub-arrays, allowing for selective access and power management to reduce active and leakage power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If multiple memory blocks are used to reduce power consumption by powering up only the active block, then power consumption is reduced, but the area increases due to added peripheral circuitry for each memory block
Solution Approach 1:
The memory is divided into multiple sub-arrays that can be independently powered. Each sub-array is a segment of the overall memory structure, allowing selective activation based on access patterns. This segmentation enables the system to power up only the necessary portions of memory while keeping other portions in a low-power state, thereby reducing overall power consumption without requiring complete duplication of peripheral circuitry for entire memory blocks.
Solution Approach 2:
Multiple sub-arrays share common peripheral circuitry including row decoders, column decoders, and sense amplifiers. By merging these peripheral resources across sub-arrays, the patent avoids the area penalty associated with duplicating full peripheral circuitry for each memory block. The shared peripherals serve multiple sub-arrays, reducing the total area while still enabling selective power management of individual sub-arrays.
2Loss of energy
If multiple memory blocks are used to reduce power consumption, then active power is reduced, but leakage current increases due to more peripheral circuitry
Solution Approach 1:
By segmenting the memory into smaller sub-arrays with shared peripherals, the patent reduces the total amount of peripheral circuitry compared to using multiple independent memory blocks. This segmentation approach minimizes the source of leakage current while still enabling selective power management to reduce active power consumption.
Solution Approach 2:
The shared peripheral circuitry structure merges the peripheral resources of multiple sub-arrays into a single set of circuits. This merging dramatically reduces the total peripheral circuit area compared to having separate peripherals for each memory block, thereby reducing leakage current while maintaining the ability to selectively power sub-arrays to reduce active power.
3Area of stationary object
If a single large memory instance is used, then area is reduced, but power consumption increases
Solution Approach 1:
The single large memory is segmented into multiple sub-arrays that can be independently controlled. This segmentation allows the system to power up only the sub-arrays that are currently being accessed, rather than powering the entire large memory. This approach maintains the area efficiency of a single memory instance while achieving the power savings of selective activation.
Solution Approach 2:
The memory system dynamically adjusts which sub-arrays are powered based on access patterns. The power management circuitry monitors memory access requests and activates only the necessary sub-arrays, creating a dynamic power management scheme that adapts to workload requirements. This dynamic approach enables the single memory instance to consume less power by being selective about which portions are active at any given time.
Data Source
AI summary
A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered.