Memory Circuit Sub-Block Segmentation for Read Accuracy
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Solution Overview
Problem
Current memory circuits face challenges in efficiently storing and retrieving high-order and low-order bytes due to redundancy in memory segments and long RC delays, which affect read speed and accuracy.
Innovation Solution
A memory circuit design with three memory sub-blocks arranged side by side, where the middle sub-block shares a row decoder with adjacent sub-blocks, and each sub-block is configured to store either high-order or low-order bytes, ensuring equal numbers of memory segments and reducing redundancy, while using switch circuits and sense amplifiers to improve read accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory segments are increased to store both high-order and low-order bytes, then storage capacity is improved, but circuit area and RC delays increase
Solution Approach 1:
The memory block is segmented into three sub-blocks (first, second, and third sub-blocks) where the first and third sub-blocks store high-order bytes and the second sub-block stores low-order bytes. This segmentation allows efficient use of memory segments by dedicating specific sub-blocks to specific byte types, reducing the total number of segments needed while maintaining storage capacity.
Solution Approach 2:
The first and third sub-blocks serve dual purposes by both storing high-order bytes and sharing row decoders with adjacent sub-blocks. The second sub-block similarly stores low-order bytes and shares row decoders. This multi-functionality reduces the overall number of row decoders needed, decreasing circuit area and RC delays.
2Measurement precision
If more memory segments are used to avoid redundancy, then read accuracy is improved, but RC delays increase
Solution Approach 1:
By segmenting the memory block into three sub-blocks with specific assignments for high-order and low-order bytes, the patent ensures that each byte type is stored in dedicated segments. This segmentation prevents wrong bit line activation during read operations, improving read accuracy while limiting the number of segments activated simultaneously, thus reducing RC delays.
Solution Approach 2:
The row decoder acts as an intermediary that selectively activates only the necessary memory segments based on the address inputs. By controlling which segments are activated through the row decoder, the system achieves accurate byte retrieval while minimizing the number of simultaneously active segments, thereby reducing RC delays.
3Measurement precision
If memory segments are increased to prevent wrong bit line activation, then read accuracy is improved, but device complexity increases
Solution Approach 1:
The memory block is divided into three sub-blocks with clear functional assignments, and each sub-block shares row decoders with adjacent sub-blocks. This segmentation strategy ensures that only the necessary segments are activated for each read operation, preventing wrong bit line activation while avoiding the need for excessive memory segments, thus maintaining manageable device complexity.
Solution Approach 2:
Adjacent sub-blocks share row decoders, merging the decoding functionality to reduce the total number of row decoders required. This merging approach prevents wrong bit line activation by ensuring proper address decoding while reducing device complexity by eliminating redundant decoder circuits.
4Ease of manufacture
If circuit area is reduced by sharing row decoders, then manufacturing efficiency is improved, but read speed may be affected
Solution Approach 1:
Adjacent sub-blocks share row decoders, merging the decoding functionality to reduce the total number of row decoders required. This reduces circuit area and improves manufacturing efficiency. The shared row decoders are designed to handle multiple sub-blocks simultaneously, ensuring that read speed is maintained despite the sharing arrangement.
Data Source
AI summary
The present disclosure provides a memory circuit and a memory. The memory circuit at least includes a plurality of memory blocks. Each of the memory blocks includes a first memory sub-block, a second memory sub-block, and a third memory sub-block arranged in sequence; the second memory sub-block includes a first memory unit and a second memory unit; the first memory sub-block and the first memory unit are configured to store high-order bytes; the second memory unit and the third memory sub-block are configured to store low-order bytes; and in an arrangement direction of memory sub-blocks, different memory units that are arranged side by side have different block selection addresses.